Abstract: A method for manufacturing a display panel is provided, the method including forming a semiconductor pattern on a base layer, applying at least one insulation layer on the semiconductor pattern, and applying a control electrode on the insulation layer so as to overlap at least a portion of the semiconductor pattern. The applying of the control electrode includes depositing molybdenum to form a preliminary electrode layer, forming a photoresist pattern on the preliminary electrode layer, and applying an etching gas to dry-etch the preliminary electrode layer. In an embodiment, in the dry-etching, the etching gas may include a nitrogen trifluoride gas, an oxygen gas, and a chlorine gas. Accordingly, it is possible to implement a manufacturing process of an eco-friendly display panel while increasing the yield and reliability of the display panel manufacturing process.

Abstract: Gate-all-around transistor devices and methods for manufacturing the same are provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isolation regions comprising an isolation material. The substrate further includes a buffer region formed in the substrate, the buffer region separating adjacent isolation regions. The semiconductor device further includes a plurality of fins, each fin formed on a corresponding isolation region of the plurality of isolation regions. Each fin includes a buffer layer contacting the isolation material and a plurality of silicon layers and a plurality of silicon germanium layers alternatingly arranged in a plurality of stacked pairs on the buffer layer.

Abstract: An integrated circuit includes a dielectric layer located over one or more metal interconnect layers. The dielectric layer includes selective regions of implanted stress-setting dopants to provide different stress profiles in the dielectric layer to counteract the stress imparted from package structures. Accordingly, the effect of the stress imparted by package structures in a substrate can be negated by the placement of stress-setting dopants in selective areas of the dielectric layer.

Abstract: Some embodiments relate to an integrated device including a first thin film transistor (TFT) arranged over a substrate; a second TFT arranged over the substrate; a metal barrier layer arranged over the second TFT, where the metal barrier layer is configured to block incident radiation from reaching the second TFT; a Fresnel lens arranged over the first TFT, where the Fresnel lens is configured to focus incident radiation towards the first TFT; and where the first TFT and the second TFT are configured to be coupled to a differential amplifier, the differential amplifier being operable to detect the incident radiation by comparison of a first leakage current from the first TFT to a second leakage current from the second TFT.

Abstract: A display panel and a display apparatus. The display panel includes: a base plate, an interconnection structure including at least two connection blocks and connection lines for connecting the at least two connection blocks; and a plurality of first sub-pixels located at a side of the interconnection structure away from the base plate and each including a first electrode, a first light-emitting structure and a second electrode stacked in sequence along a direction away from the interconnection structure; in which at least a part of the first electrode is located at a side of the connection block away from the base plate and electrically connected with the connection block, and an orthographic projection of the connection block on the base plate is at least partially staggered with an orthographic projection of the first light-emitting structure on the base plate.

Abstract: A monolithic focal plane array (FPA) device and method of fabrication. The method can include forming monolithic photodetectors or FPAs by heteroepitaxial growth of III-V PINs, APDs, or other photodetector devices in etched recesses of a Si-based read-out integrated circuit (ROIC) wafer. In a single-color device example, a wavelength configuring buffer layer and photodetector are grown within the etched recesses using compound semiconductor materials to enable infrared detection at desired wavelength(s). Depending on the application, this growth can be done on a graded compliant buffer layer and/or a selectively transparent buffer layer. And, semiconductor detectors can be incorporated to detect visible and NIR wavelengths in a dual-color device example. Further, the resulting devices can be configured as pixels in a sensor array device coupled to the ROIC device.

Abstract: A method for manufacturing an image sensing device includes forming a grid structure over a semiconductor substrate to provide spaces for disposing color filters, forming first color filters, second color filters, third color filters in some of the spaces defined by the grid structure, the first color filters, the second color filters, and the third color filters configured to transmit light corresponding to a first color, a second color, and a third color, respectively, forming an overcoating layer to cover the first to third color filters, the overcoating layer filling remaining spaces of the spaces defined by the grid structure, the remaining spaces free of the first to third color filters, and forming microlenses over the overcoating layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wraparound gate structure and methods of manufacture. The structure includes: a channel region comprising semiconductor material; an isolation structure surrounding the channel region; a divot within the isolation structure; and a gate structure comprising gate material within the divot and surrounding the channel region.

Abstract: A semiconductor device includes a semiconductor substrate, an active region on the semiconductor substrate and including a first semiconductor material, an isolation layer on the semiconductor substrate and a side surface of the active region, a first gate structure in a first gate trench crossing the active region, a second gate structure in a second gate trench in the isolation layer, the second gate structure being parallel to the first gate structure and adjacent to the active region, a semiconductor layer covering at least a part of the side surface of the active region, the semiconductor layer including a second semiconductor material different from the first semiconductor material, and at least a part of the semiconductor layer being between the active region and the second gate structure, and source/drain regions in the active region on opposite sides of the first gate trench.

Abstract: A solid-state imaging element with pixel transistors and wires capable of efficiently outputting and transferring a pixel signal from a stacked photoelectric conversion film while suppressing an increase in manufacturing cost, and a manufacturing method thereof are provided.

Abstract: An image sensing device and a method for forming the same are disclosed. The image sensing device includes a first substrate, first photoelectric conversion elements formed in the first substrate and configured to generate photocharges in response to a reception of light, a second substrate formed over the first substrate, and second photoelectric conversion elements formed in the second substrate and configured to generate photocharges in response to a reception of light, the second photoelectric conversion elements contacting corresponding the first photoelectric conversion elements, respectively.

Abstract: In an intermediate region between an active region and an edge termination region, on a front surface of a semiconductor substrate, a gate polysilicon wiring layer is provided via an insulating layer in which a gate insulating film and a field oxide film are stacked sequentially. An inner peripheral end of the field oxide film is positioned directly beneath the gate polysilicon wiring layer, which extends inward from the field oxide film and terminates on the gate insulating film. At the surface of the insulating layer directly beneath the gate polysilicon wiring layer, on the inner peripheral end of the field oxide film, a drop is formed by a difference in thickness due to whether the field oxide film is present. A distance from the drop to a contact hole of the active region is 21 ?m or less.

Abstract: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator.

Abstract: Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.

Abstract: Provided is a semiconductor structure and a formation method therefor. The semiconductor structure includes: a gate structure located on a substrate. The gate structure includes at least two gate conductive layers; the at least two gate conductive layers have the same components and different characteristic parameters; and the characteristic parameter includes at least one of thickness, component content or shape.

Abstract: An image sensor device includes a substrate, a deep-trench isolation structure, an oxide layer, a light blocking structure, and an adhesion layer. The substrate has a photosensitive region. The deep-trench isolation structure is in the substrate and adjacent the photosensitive region. The oxide layer is over the photosensitive region and the deep-trench isolation structure. The light blocking structure is over the oxide layer. A bottom portion of the light blocking structure is embedded in the oxide layer. The adhesion layer is between the light blocking structure and the oxide layer. The adhesion layer extends beyond a sidewall of a top portion of the light blocking structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.

Abstract: A microelectronic structure including a first nanosheet transistor including a first backside metal line that has a first width as measure along a bottom surface of the first backside metal line and the first backside metal line has a second width as measure along a top surface of the first backside metal line. A second backside metal line that includes a second backside contact that is connected to the second source drain and the second backside metal line has a third width as measure along a bottom surface of the second backside metal line. The second backside metal line has a fourth width as measure along a top surface of the second backside metal line. The first width is larger than the second width and the third width is larger than the fourth width.

Abstract: Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.