Patents Examined by Nelson Garces
  • Patent number: 11309225
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Patent number: 11309393
    Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-yeon Lee, Jin-wook Lee, Min-chan Gwak, Kye-Hyun Baek, Hong-bae Park
  • Patent number: 11309426
    Abstract: An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: April 19, 2022
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 11302735
    Abstract: An image sensor includes a substrate configured to include a plurality of pixels, each pixel including a photodiode formed in the substrate, a plurality of deep trench isolation (DTI) structures formed in the substrate to optically isolate each of the plurality of pixels from neighboring pixels, and a transparent electrode layer arranged over the photodiode and electrically connected to the plurality of DTI structures.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Yun Hui Yang
  • Patent number: 11282939
    Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Hoon Lee, Wan Don Kim, Jong Ho Park, Sang Jin Hyun
  • Patent number: 11282874
    Abstract: The invention discloses a global shutter CMOS image sensor. Each pixel unit of the global shutter CMOS image sensor includes a photo diode, a storage region and a first reset region, wherein the photo diode includes a first photosensitive doped region; a gate structure of a first transfer transistor is formed between the storage region and the first photosensitive doped region; a gate structure of a global shutter transistor is formed between the first reset region and the first photosensitive doped region; and inhomogeneous potentials are formed in the first photosensitive doped region through a doping structure. According to the invention, photo-induced carriers in the PDs of the pixel units, especially photo-induced carriers in the PDs of large pixel units, can be simultaneously and completely transferred to the storage region and the first reset region, and the overall performance of the device is improved.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 22, 2022
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Haoyu Chen, Zhi Tian, Qiwei Wang, Hua Shao
  • Patent number: 11271149
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second precessional spin current ferromagnetic layer separated by a nonmagnetic precessional spin current insertion layer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 8, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Bartlomiej Adam Kardasz, Mustafa Michael Pinarbasi
  • Patent number: 11264471
    Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 11264587
    Abstract: A display apparatus includes a substrate having a first region and a second region surrounding the first region. An insulating part is disposed above the substrate, covering the first region and the second region, and comprising a first opening portion in the second region. A dam part is disposed above the insulating pan in the second region and surrounds a periphery of the first opening portion. A first organic insulating layer is disposed above the insulating part and covers an inner surface of the first opening portion. An organic light-emitting device is disposed above the insulating part in the first region and comprises a pixel electrode. An encapsulation layer is disposed above the insulating part in both the first region and the second region. The encapsulation layer covers the organic light-emitting device.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jonghyun Choi, Hyunsun Park
  • Patent number: 11257722
    Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki Tanemura, Etsuko Kamata, Hiromi Sawai, Daisuke Matsubayashi
  • Patent number: 11257835
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, rows of memory openings vertically extending through the alternating stack, memory opening fill structures located within a first subset of the rows of memory openings, where each of the memory opening fill structures includes a respective memory film and a respective vertical semiconductor channel extending through an opening at a bottom portion of the respective memory film and contacting a respective underlying semiconductor material portion, and dummy memory opening fill structures located within a second subset of the rows of memory openings that do not belong the first subset, where each of the dummy memory opening fill structures includes a respective dummy memory film and a respective dummy vertical semiconductor channel that is electrically isolated from a respective underlying semiconductor material portion by a bottom portion of the respective dummy memory film.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Liang Li, Chao Xu, Zhe Song
  • Patent number: 11257924
    Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Chun-Sheng Liang, Ming-Chi Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Hsin-Che Chiang
  • Patent number: 11257723
    Abstract: An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyun Kim, Sunwon Kang, Hogeon Song, Kyung Suk Oh
  • Patent number: 11233076
    Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 25, 2022
    Assignee: ARGO AI, LLC
    Inventors: Mark Allen Itzler, Brian Piccione, Xudong Jiang, Krystyna Slomkowski
  • Patent number: 11217549
    Abstract: A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 4, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lianbin Liu, Hengzhen Liang, Chuanyan Lan, Guoqiang Wu
  • Patent number: 11217599
    Abstract: A plurality of select transistors are formed in a first region of a semiconductor substrate, a plurality of memory transistors are formed in a second region of the semiconductor substrate, and a drain region of the select transistor and a source region of the memory transistor are electrically connected to form a memory cell. Here, the first region and the second region are arranged with each other in a gate width direction of the select transistor and the memory transistor.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideaki Yamakoshi
  • Patent number: 11217620
    Abstract: A more preferable pixel for detecting a focal point may be formed by using a photoelectric converting film. A solid-state image sensor includes a first pixel including a photoelectric converting unit formed of a photoelectric converting film and first and second electrodes which interpose the same from above and below in which at least one of the first and second electrodes is a separated electrode separated for each pixel, and a second pixel including the photoelectric converting unit in which the separated electrode is formed to have a planar size smaller than that of the first pixel and a third electrode extending at least to a boundary of the pixel is formed in a region which is vacant due to a smaller planar size. The present disclosure is applicable to the solid-state image sensor and the like, for example.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 4, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yukio Kaneda
  • Patent number: 11211492
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Carlos H. Diaz, Chun Hsiung Tsai, Yu-Ming Lin
  • Patent number: 11211389
    Abstract: Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Sheng Fen Chiu, Fansheng Kung
  • Patent number: 11211416
    Abstract: A photoelectric conversion apparatus includes a semiconductor layer having a front surface and a back surface and in which a plurality of photoelectric conversion portions is provided between the front surface and the back surface, a wiring structure arranged on the front surface side of the semiconductor layer, a separation portion arranged between the plurality of photoelectric conversion portions and formed by a trench continuing from the back surface, a first light shielding portion arranged above the semiconductor layer on the back surface side so as to overlap the separation portion, and a second light shielding portion arranged above the semiconductor layer on the back surface side so as to face the first light shielding portion via a region located above at least one photoelectric conversion portion among the plurality of photoelectric conversion portions.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: December 28, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Toshiyuki Ogawa, Nobuhiko Sato, Masaki Kurihara, Yoichi Wada