Patents Examined by Nelson Garces
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Patent number: 11664402Abstract: A method of manufacturing a semiconductor device, includes forming a trench in a semiconductor substrate having a first face and a second face by processing the first face of the semiconductor substrate, the trench including a first portion and a second portion located between the first portion and a plane including a first face, filling an insulator in the second portion such that a space remains in the first portion and the trench is closed, and forming a plurality of elements between the first face and the second face, wherein the space and the insulator form element isolation.Type: GrantFiled: March 5, 2020Date of Patent: May 30, 2023Assignee: CANON KABUSHIKI KAISHAInventor: Kazuo Kokumai
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Patent number: 11664403Abstract: An image sensor device includes a substrate, a deep-trench isolation structure, a buffer layer, and a light blocking structure. The substrate has a photosensitive region. The deep-trench isolation structure is in the substrate and adjacent the photosensitive region. The buffer layer is over the photosensitive region and the deep-trench isolation structure. The light blocking structure is over the buffer layer. A bottom portion of the light blocking structure is embedded in the buffer layer.Type: GrantFiled: June 12, 2020Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zen-Fong Huang, Fu-Cheng Chang
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Patent number: 11664413Abstract: A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.Type: GrantFiled: January 6, 2021Date of Patent: May 30, 2023Assignee: SK hynix Inc.Inventors: Dong Ik Suh, Se Ho Lee
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Patent number: 11646334Abstract: A semiconductor device includes a semiconductor layer, a metal layer disposed above a surface of the semiconductor layer, a first barrier portion that covers a first portion of a surface of the metal layer, a second barrier portion that covers a second portion of the surface of the metal layer, an insulating film that covers the metal layer and the first and second barrier portions; and a metal member that is disposed in an opening portion provided in the insulating film, the metal member positioned on a third portion of the surface of the metal layer that is between the first portion and the second portion. A part of the insulating film is disposed between the metal member and the first barrier portion and between the metal member and the second barrier portion.Type: GrantFiled: March 2, 2021Date of Patent: May 9, 2023Assignee: CANON KABUSHIKI KAISHAInventor: Takayuki Suzuki
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Patent number: 11637235Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.Type: GrantFiled: January 16, 2020Date of Patent: April 25, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sumio Ikegawa, Han Kyu Lee, Sanjeev Aggarwal, Jijun Sun, Syed M. Alam, Thomas Andre
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Patent number: 11631765Abstract: A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.Type: GrantFiled: December 28, 2020Date of Patent: April 18, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Akimasa Kinoshita
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Patent number: 11621287Abstract: An optical sensor device and a method for forming the same are provided, including forming a curable transparent material on a substrate, wherein the substrate has a plurality of optical sensor units therein; providing a transparent template, which has a plurality of concaves; imprinting the curable transparent material with the transparent template to form a plurality of convexes corresponding to the plurality of concaves; and curing the curable transparent material to form a transparent layer having a micro-lens array. The step of curing the curable transparent material includes adhering the transparent template to the curable transparent material to act as a cover plate for the optical sensor device.Type: GrantFiled: April 16, 2020Date of Patent: April 4, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Hsin-Hui Lee, Han-Liang Tseng, Hsueh-Jung Lin
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Patent number: 11621260Abstract: A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate.Type: GrantFiled: May 8, 2020Date of Patent: April 4, 2023Assignee: ROHM CO., LTD.Inventor: Hiroyuki Kaneda
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Patent number: 11616061Abstract: A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.Type: GrantFiled: November 19, 2018Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Yi Tsai, Chun-Liang Lai, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
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Patent number: 11616015Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.Type: GrantFiled: December 18, 2020Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru
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Patent number: 11610926Abstract: An image sensing device that includes a reinforced structure is disclosed. The image sensing device includes a semiconductor substrate structured to include a pixel region including a plurality of unit pixels and a peripheral region located outside the pixel region, a plurality of microlenses disposed over the semiconductor substrate in the pixel region, a structural reinforcement layer disposed over the semiconductor substrate in the peripheral region, and a lens capping layer structured to cover the microlenses and at least of the structural reinforcement layer. The structural reinforcement layer includes a plurality of fingers each finger vertically structured to have a rounded upper end and laterally extend to have a predetermined length toward the pixel region. The fingers are consecutively arranged and connected to each other in a lateral direction, and side surfaces of fingers are in contact with side surfaces of immediately adjacent fingers.Type: GrantFiled: April 12, 2021Date of Patent: March 21, 2023Assignee: SK hynix Inc.Inventors: Yun Hui Yang, Tae Gyu Park, Dong Bin Park
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Patent number: 11600712Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.Type: GrantFiled: November 22, 2019Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sanghyun Jo, Sangwook Kim, Yunseong Lee, Jinseong Heo
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Patent number: 11600616Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure.Type: GrantFiled: September 27, 2019Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gerben Doornbos, Mark Van Dal
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Patent number: 11562992Abstract: There is provided an image module package including a substrate, a photo sensor chip, a molded transparent layer and a glass filter. The substrate has an upper surface. The photo sensor chip is attached to the upper surface of the substrate and electrically connected to the substrate. The molded transparent layer covers the photo sensor chip and a part of the upper surface of the substrate, wherein a top surface of the molded transparent layer is formed with a receptacle opposite to the photo sensor chip. The glass filter is accommodated in the receptacle.Type: GrantFiled: January 22, 2021Date of Patent: January 24, 2023Assignee: PIXART IMAGING INC.Inventors: Chee-Pin T'Ng, Sai-Mun Lee
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Patent number: 11563167Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.Type: GrantFiled: July 12, 2019Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
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Patent number: 11557145Abstract: A photo sensor, a manufacturing method thereof, and a display panel are disclosed. By an ion implantation method forming an N-type region and a P-type region on a surface of polycrystalline silicon in a same layer respectively, compatibility with an ion implantation process is ensured, while covering a layer of an amorphous silicon photosensitive layer on the polycrystalline silicon enhances light absorption ability and can increase photo-generated electron-hole pairs. Furthermore, built-in electric fields exist on a horizontal direction and a vertical direction, which can more effectively separate the electron-hole pairs to enhance photo-generated electric current to improve accuracy of fingerprint recognition.Type: GrantFiled: April 2, 2020Date of Patent: January 17, 2023Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Juncheng Xiao, Fei Ai, Jiyue Song
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Patent number: 11557584Abstract: An integrated circuit (IC) includes: a first cell including an input pin and an output pin extending in a first direction; a second cell adjacent to the first cell in the first direction and including an input pin and an output pin extending in the first direction; a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and a first wire extending in the first direction, overlapping the first cell isolation layer, and being connected to the output pin of the first cell and the input pin of the second cell, wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.Type: GrantFiled: November 30, 2020Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yongcheul Kim, Jooyeon Kwon, Sangdo Park
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Patent number: 11557617Abstract: An image sensing device is disclosed. The image sensing device includes a pixel array including a plurality of unit pixels, each of which is configured to generate a pixel signal in response to incident light.Type: GrantFiled: July 28, 2020Date of Patent: January 17, 2023Inventor: Min Su Cho
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Patent number: 11557620Abstract: A high k passivation layer, an anti-reflective coating layer, and a buffer layer are disposed over semiconductor substrate including photodiodes formed therein. Trenches are etched into the semiconductor substrate through the buffer layer, anti-reflective coating layer, and the high k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high k passivation layer lines an interior of the trenches in the semiconductor substrate. An adhesive and barrier layer is deposited over the high k passivation layer that lines the interior of the trenches. A deep trench isolation (DTI) structure is formed with conductive material deposited into the trenches over the adhesive and barrier layer to fill the trenches. A grid structure is formed over the DTI structure and above a plane of the buffer layer. The grid structure is formed with the conductive material.Type: GrantFiled: March 30, 2021Date of Patent: January 17, 2023Assignee: OmniVision Technologies, Inc.Inventors: Seong Yeol Mun, Yibo Zhu, Keiji Mabuchi
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Patent number: 11548781Abstract: A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.Type: GrantFiled: November 16, 2018Date of Patent: January 10, 2023Assignee: SCIOSENSE B.V.Inventors: Casper Van Der Avoort, Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Coen Tak