Patents Examined by Nelson Garces
  • Patent number: 10964706
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton J. deVilliers
  • Patent number: 10950560
    Abstract: Lands (11c and 11d) are parts of base plates (104c and 104d), and electrodes of a shunt resistor (103U) are put on and connected to the lands (11c and 11d). Slits (130 and 131) are formed in the lands (11c and 11d) to separate a main electric circuit in which a main current flows and control terminals (123 and 124) with which the electric potentials of the electrodes of the shunt resistor (103U) are detected. Leading end portions of the slits (130 and 131) extend to the vicinity of the electrodes of the shunt resistor (103U).
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsuhiko Omae, Masayuki Funakoshi, Kensuke Takeuchi
  • Patent number: 10950686
    Abstract: The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1. The side T1a and the side of T2a are exposed from the opening portion OP1 and OP2 of the solder resist layer SR1 respectively, and outer peripheries of terminal patterns TP1 and TP2 other than sides T1a and T2a are not exposed from opening portions OP1 and OP2. The opening portion OP1 and the opening portion OP2 are separated from each other. The electrode E1 of the capacitor C1 is soldered to the terminal pattern TP1 exposed from the opening portion OP1, and the electrode E2 of the capacitor C1 is soldered to the terminal pattern TP2 exposed from the opening portion OP2.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Karashima
  • Patent number: 10937901
    Abstract: Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 2, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Akimasa Kinoshita
  • Patent number: 10937789
    Abstract: A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Muthumanickam Sankarapandian, Donald F. Canaperi, Keith E. Fogel
  • Patent number: 10937773
    Abstract: There is provided an image module package including a substrate, a photo sensor chip, a molded transparent layer and a glass filter. The substrate has an upper surface. The photo sensor chip is attached to the upper surface of the substrate and electrically connected to the substrate. The molded transparent layer covers the photo sensor chip and a part of the upper surface of the substrate, wherein a top surface of the molded transparent layer is formed with a receptacle opposite to the photo sensor chip. The glass filter is accommodated in the receptacle.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 2, 2021
    Assignee: PIXART IMAGING INC.
    Inventors: Chee-Pin T'ng, Sai-Mun Lee
  • Patent number: 10923595
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1?x?yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01?x?0.1.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Carlos H. Diaz, Chun Hsiung Tsai, Yu-Ming Lin
  • Patent number: 10892291
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Patent number: 10886271
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Fee Li Lie, Eric R. Miller, Sean Teehan
  • Patent number: 10886217
    Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru
  • Patent number: 10886265
    Abstract: An embodiment includes an apparatus comprising: a dielectric material including fixed charges, the fixed charges each having a first polarity; a channel comprising a channel material, the channel material including a 2-dimensional (2D) material; a drain node; and a source node including a source material, the source material including at least one of the 2D material and an additional 2D material; wherein the source material: (a) includes charges each having a second polarity that is opposite the first polarity, (b) directly contacts the dielectric material. Other embodiments are described herein.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Uygar Avci, Ian Young
  • Patent number: 10865101
    Abstract: Discharge circuits, devices and methods. In some embodiments, a MEMS device can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS device can further include a discharge circuit implemented relative to the electromechanical assembly. The discharge circuit can be configured to provide a preferred arcing path during a discharge condition affecting the electromechanical assembly. The MEMS device can be, for example, a switching device, a capacitance device, a gyroscope sensor device, an accelerometer device, a surface acoustic wave (SAW) device, or a bulk acoustic wave (BAW) device. The discharge circuit can include a spark gap assembly having one or more spark gap elements configured to facilitate the preferred arcing path.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 15, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jerod F. Mason, Dylan Charles Bartle, David Scott Whitefield, David T. Petzold, Dogan Gunes, Paul T. Dicarlo
  • Patent number: 10867924
    Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin
  • Patent number: 10868132
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh, Carlos H. Diaz
  • Patent number: 10861842
    Abstract: An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10861873
    Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 8, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jee-Yeon Kim, Kwang-Ho Kim, Fumiaki Toyama
  • Patent number: 10854518
    Abstract: A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10847604
    Abstract: A capacitor includes a first metal layer over a substrate, a second metal layer over the first metal layer, and first and second cells. Each cell is electrically coupled to first and second buses. Each cell includes first plurality and second plurality of fingers in the first metal layer, and third plurality and fourth plurality of fingers in the second metal layer. The first plurality of fingers extend in a first direction parallel to a top surface of the substrate and are electrically coupled to the first bus. The second plurality of fingers extend in the first direction and are electrically coupled to the second bus. The third plurality of fingers extend in a second direction parallel to the top surface of the substrate and are electrically coupled to the first bus. The second direction is different from the first direction. The fourth plurality of fingers extend in the second direction and are electrically coupled to the second bus.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 24, 2020
    Assignee: XILINX, INC.
    Inventors: Jing Jing, Shuxian Wu, Parag Upadhyaya
  • Patent number: 10847622
    Abstract: A field effect transistor includes a channel made of germanium and a source/drain portion. The source/drain portion includes a germanium layer, an interfacial epitaxial layer over the germanium layer, a semiconductor layer over the interfacial epitaxial layer, and a conducting layer over the semiconductor layer. The interfacial epitaxial layer contains germanium and an element from the semiconductor layer and has a thickness in a range from about 1 nm to about 3 nm.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Martin Christopher Holland, Blandine Duriez
  • Patent number: 10847549
    Abstract: A thin film transistor array including thin film transistor elements including an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a channel region formed between the source electrode and the drain electrode, the thin film transistor elements being arrayed in a matrix, a disconnection pattern including an insulating material and formed in stripes extending over the thin film transistor elements, the disconnection pattern having a maximum film thickness of 200 nm-3000 nm, and a semiconductor pattern formed in stripes perpendicular to the disconnection pattern and extending over the channel region of the thin film transistor elements, the semiconductor pattern being disconnected at an intersection with the disconnection pattern.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: November 24, 2020
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Makoto Nishizawa