Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

Abstract: Apparatuses including semiconductor layout to mitigate local layout effects are disclosed. An example apparatus includes a plurality of standard cells each including an active region, an isolation region adjacent the active region, and a first gate structure disposed on the active region and the isolation region. The first gate structure includes a first gate portion disposed on the active region, and a first contact portion disposed on the isolation region. The apparatus further includes a second gate structure disposed on the active region and the isolation region. The second gate structure includes a second gate portion disposed on the active region, and a second contact portion disposed on the isolation region. In the apparatus, a distance between a first contact point and the first gate portion is substantially equal to a distance between a second contact point and the second gate portion.

Abstract: In a solid-state imaging device, a photoelectric conversion unit, a transfer transistor, and at least a part of electric charge holding unit, among pixel constituent elements, are disposed on a first semiconductor substrate. An amplifying transistor, a signal processing circuit other than a reset transistor, and a plurality of common output lines, to which signals are read out from a plurality of pixels, are disposed on a second semiconductor substrate.

Abstract: Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.

Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

Abstract: New types, structures, and arrangements of capacitor networks for harmonic control and other purposes are presented. In one example, an integrated device includes a capacitor network and one or more power devices. The capacitor network includes a bond pad and metal-insulator-metal (MIM) capacitors. The capacitors include a first metal layer, a second metal layer, an insulator layer between the first and second metal layers, and one or more through-substrate vias. The first metal layer is coupled to the bond pad, and the second metal layer is coupled to a ground plane on a bottom side of the substrate by the vias. A number of capacitors can be arranged around the bond pad in the capacitor network for a tailored capacitance. A matching network in the integrated device can incorporate the capacitor network to reduce loss, provide better harmonic termination, and achieve better phase alignment for the power devices.

Abstract: A color filter layer and a display device are provided. A material of the color filter layer includes a dye, a polymer resin, a monomer, a photoinitiator, and a solvent. A material of the dye is one of a core-shell material or a titanium dioxide material. The shell material includes an organic polymer, and the core material is an inorganic fluorescent material. The shell material covers the core material, and the inorganic fluorescent material includes a europium-doped compound.

Abstract: A moiré pattern imaging device includes a light-transmissive film and a light-shielding film. The light-transmissive film includes a plurality of imaging units and a light-incident surface and a light-emergent surface opposite to each other. The plurality of imaging units are disposed on the light-incident surface, the light-emergent surface, or a combination thereof and are arranged in two dimensions to form an imaging unit array. The light-shielding film includes a plurality of light-transmissive regions. The light-transmissive regions are arranged in two dimensions to form a light-transmissive array, and the light-shielding film is overlaid on the light-incident surface or the light-emergent surface. The light-transmissive array corresponds to the imaging unit array. The imaging unit array and the light-transmissive array together form a moiré pattern effect to generate an image magnification effect.

Abstract: A display device including a base member, a circuit layer, a display layer, a thin film encapsulation layer, and a touch sensor layer. The base member includes a first area and a second area disposed adjacent to the first area. The circuit layer is disposed on the base member to cover the first area and to expose the second area. The display layer is disposed on the circuit layer to display an image. The thin film encapsulation layer is disposed on the display layer. The touch sensor layer is disposed on the thin film encapsulation layer and includes an organic layer extending from an upper portion of the thin film encapsulation layer to cover at least a portion of the exposed second area.

Abstract: The present disclosure provides a semiconductor structure, and a method for fabricating a semiconductor structure, the method includes forming a bottom electrode, forming a magnetic tunneling junction (MTJ) layer over the bottom electrode, wherein the MTJ layer includes a first material, forming a top electrode over the MTJ layer, forming a first dielectric layer over the top electrode and the MTJ layer, and patterning the MTJ layer to form an MTJ, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material, and the residue is apart from the bottom electrode, forming a second dielectric layer over the first dielectric layer to encapsulate the residue, and forming an insulation layer surrounding the second dielectric layer.

Abstract: The present application provides a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region, and including a first recess extending into the semiconductor substrate and disposed in the array region; an isolation structure surrounded by the semiconductor substrate and disposed in the peripheral region; and a word line disposed within the first recess, wherein the word line includes an insulating layer conformal to the first recess and a conductive member surrounded by the insulating layer, and the conductive member includes a second recess extending into the conductive member and toward the semiconductor substrate. A method of manufacturing the memory device is also disclosed.

Abstract: A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.

Abstract: A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.

Abstract: A sensing apparatus including a sensing device, a light-transmitting protective layer, a light-shielding layer, a light-transmitting adhesive layer and a light guide device is provided. The light-transmitting protective layer is disposed on the sensing device. The light-shielding layer is disposed on the light-transmitting protective layer. The light shielding layer has a pinhole corresponding to the sensing device. The light-transmitting adhesive layer is disposed on the light-transmitting protective layer and at least in the pinhole. The light guide device is disposed on the light-transmitting adhesive layer and corresponds to the pinhole. There is a gap between the light guide device and the light shielding layer; and/or the refractive index of the light-transmitting adhesive layer is greater than the refractive index of the light guide device.

Abstract: A method of forming a semiconductor memory device, the semiconductor memory device includes a plurality of active areas, a shallow trench isolation, a plurality of trenches and a plurality of gates. The active areas are defined on a semiconductor substrate, and surrounded by the shallow trench isolation. The trenches are disposed in the semiconductor substrate, penetrating through the active areas and the shallow trench isolation, wherein each of the trenches includes a bottom surface and a saddle portion protruded therefrom in each active areas. The gates are disposed in the trenches respectively.

Abstract: A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.

Abstract: A memory and a method for manufacturing the same are provided. The memory includes: a substrate including an isolation structure and an active area between adjacent isolation structures; a first gate structure, the first gate structure locates in a first groove of the isolation structure, includes a first gate filled in the first groove, and the first gate includes a first conductive layer filled at the bottom of the first groove and a second conductive layer, the second conductive layer locates above the first conductive layer, and the work function of the material of the first conductive layer is greater than that of the material of the second conductive layer; a second gate structure, located in the second groove of the active area, includes a second gate filled in the second groove, and the material of the second gate is the same as that of the second conductive layer.

Abstract: A fingerprint sensor includes: a light sensing layer including a light sensing element; and an optical layer including a plurality of light transmitting areas, a light blocking area, a light transmitting member disposed in the plurality of light transmitting areas, a light blocking member disposed in the light blocking area, and a planarization member disposed on the light blocking member, wherein the light blocking area surrounds the plurality of light transmitting areas, wherein the light transmitting member includes a first organic material, wherein the light blocking member includes a second organic material, and wherein the planarization member includes a third organic material and a positive-type photosensitive material.

Abstract: The present disclosure relates to compounds of Formula (I)-(V) as compounds capable of emitting delayed fluorescence and uses of these compounds in organic light-emitting diodes.

Abstract: An imaging apparatus performs a global electronic shutter operation. During an exposure period for acquiring one frame, the imaging apparatus transfers electric charges accumulated in a first period from a photoelectric conversion portion to a holding portion. When a second period has elapsed since an end time of the first period, the holding portion holds both electric charges generated in the first period and electric charges generated in the second period. A plurality of pixels included in the imaging apparatus includes a first pixel and a second pixel each having a different saturation charge quantity of the photoelectric conversion portion included in each pixel.