Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.

Abstract: In a semiconductor device, when a printed circuit board is pressed against a bottom part of a case with an adhesive interposed therebetween, the back surface of the printed circuit board is supported by projections formed on the bottom part. Since the gap between the printed circuit board and the bottom part is maintained to have substantially the same height as the projections, the adhesive pressed by the printed circuit board does not spread excessively. At each edge of the printed circuit board in the long-side direction, the end of the adhesive is aligned with or extends slightly beyond the edge. In the short-side direction, the adhesive extends beyond each edge of the printed circuit board, but does not extend over the front surface of the printed circuit board, internal connection terminals, or the front surface of a ceramic circuit board.

Abstract: An active semiconductor device, such as a laterally diffused metal oxide semiconductor (LDMOS) transistor, includes a substrate having a substrate resistivity of at least 1 kohm-cm. An active area of the active semiconductor device is formed in the substrate. A doped implant region is formed in the substrate surrounding the active area of the active semiconductor device and a field oxide region is formed over the doped implant region. The doped implant region may include a boron dopant. Methodology entails forming the doped implant region prior to formation of the field oxide region.

Abstract: A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. The plurality of electrode layers includes a first electrode layer connected to a first wire in the first wiring layer and a second electrode layer connected to a second wire in the second wiring layer.

Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

Abstract: Disclosed are a method of manufacturing display device, an epitaxial wafer and a display device that includes a display substrate, a first sub pixel unit and a second sub pixel unit. The first sub pixel unit and the second sub pixel unit belong to same color type. The first sub pixel unit and the second sub pixel unit are formed from an epitaxial structure on the epitaxial wafer. The first sub pixel unit and the second sub pixel unit are formed and transferred to the display substrate from the epitaxial wafer. A first light emitting area of the first sub pixel unit and a second light emitting area of the second sub pixel unit are related to at least the photoluminescence measurement result of the epitaxial wafer.

Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.

Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

Abstract: A substrate packaging structure includes: a first substrate and a second substrate that are electrically connected; a plurality of conductive blocks arranged on each one of the first substrate and the second substrate, and electrically connected to each other; first and second conductive areas respectively formed on upper and side surfaces of the first substrate; a first reference conductive area formed below the upper surface of the first substrate and electrically connected to the first and second conductive areas; third and fourth conductive areas respectively formed on upper and side surfaces of the second substrate; and a second reference conductive area formed below the upper surface of the second substrate and electrically connected to the third and fourth conductive areas. The first conductive area on the first substrate is electrically connected to the third conductive area on the second substrate.

Abstract: A semiconductor device includes an elongated plate having at least a pair of grooves or protrusions, which are spaced from each other in a width direction and extend without interruption in a longitudinal direction, on a surface of the elongated plate, a semiconductor chip mounted on the surface of the elongated plate and including an element region which extends in the longitudinal direction, a resin over the semiconductor chip, the resin forming a slit that extends in the longitudinal direction of the elongated plate, leaving the element region exposed, and a transparent plate that extends in the longitudinal direction of the elongated plate and is disposed on the slit to allow light transmission.

Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Abstract: A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.

Abstract: A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

Abstract: A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.