Abstract: In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.

Abstract: A method includes at least the following steps. A material layer is formed over an image capture chip. A patterned mask layer is formed on the material layer, wherein a pattern density of the patterned mask layer varies from a central region of the patterned mask layer to a periphery region of the patterned mask layer. The material layer is polished by using the patterned mask layer as a mask to form a lens layer including a single lens portion on the image capture chip.

Abstract: Various embodiments of the present application are directed towards a semiconductor device comprising a trench capacitor, the trench capacitor comprising a plurality of lateral protrusions. In some embodiments, the trench capacitor comprises a dielectric structure over a substrate. The dielectric structure may comprise a plurality of dielectric layers overlying the substrate. The dielectric structure may comprise a plurality of lateral recesses. In some embodiments, the plurality of lateral protrusions extend toward and fill the plurality of lateral recesses. By forming the trench capacitor with the plurality of lateral protrusions filling the plurality of lateral recesses, the surface area of the capacitor is increased without increasing the depth of the trench. As a result, greater capacitance values may be achieved without necessarily increasing the depth of the trench and thus, without necessarily increasing the size of the semiconductor device.

Abstract: A field effect transistor includes a channel made of germanium and a source/drain portion. The source/drain portion includes a germanium layer, an interfacial epitaxial layer over the germanium layer, a semiconductor layer over the interfacial epitaxial layer, and a conducting layer over the semiconductor layer. The interfacial epitaxial layer contains germanium and an element from the semiconductor layer and has a thickness in a range from about 1 nm to about 3 nm.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.

Abstract: The present disclosure provides a semiconductor structure, including a magnetic tunneling junction (MTJ), a top electrode over a top surface of the MTJ, a first dielectric layer surrounding the top electrode, wherein a bottom surface of the first dielectric contacts with a top surface of the MTJ, and a second dielectric layer surrounding the first dielectric layer and the MTJ.

Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Abstract: A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor.

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.

Abstract: An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

Abstract: An image sensor includes a substrate configured to include a plurality of pixels, each pixel including a photodiode formed in the substrate, a plurality of deep trench isolation (DTI) structures formed in the substrate to optically isolate each of the plurality of pixels from neighboring pixels, and a transparent electrode layer arranged over the photodiode and electrically connected to the plurality of DTI structures.

Abstract: The invention discloses a global shutter CMOS image sensor. Each pixel unit of the global shutter CMOS image sensor includes a photo diode, a storage region and a first reset region, wherein the photo diode includes a first photosensitive doped region; a gate structure of a first transfer transistor is formed between the storage region and the first photosensitive doped region; a gate structure of a global shutter transistor is formed between the first reset region and the first photosensitive doped region; and inhomogeneous potentials are formed in the first photosensitive doped region through a doping structure. According to the invention, photo-induced carriers in the PDs of the pixel units, especially photo-induced carriers in the PDs of large pixel units, can be simultaneously and completely transferred to the storage region and the first reset region, and the overall performance of the device is improved.

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second precessional spin current ferromagnetic layer separated by a nonmagnetic precessional spin current insertion layer.

Abstract: A display apparatus includes a substrate having a first region and a second region surrounding the first region. An insulating part is disposed above the substrate, covering the first region and the second region, and comprising a first opening portion in the second region. A dam part is disposed above the insulating pan in the second region and surrounds a periphery of the first opening portion. A first organic insulating layer is disposed above the insulating part and covers an inner surface of the first opening portion. An organic light-emitting device is disposed above the insulating part in the first region and comprises a pixel electrode. An encapsulation layer is disposed above the insulating part in both the first region and the second region. The encapsulation layer covers the organic light-emitting device.

Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, rows of memory openings vertically extending through the alternating stack, memory opening fill structures located within a first subset of the rows of memory openings, where each of the memory opening fill structures includes a respective memory film and a respective vertical semiconductor channel extending through an opening at a bottom portion of the respective memory film and contacting a respective underlying semiconductor material portion, and dummy memory opening fill structures located within a second subset of the rows of memory openings that do not belong the first subset, where each of the dummy memory opening fill structures includes a respective dummy memory film and a respective dummy vertical semiconductor channel that is electrically isolated from a respective underlying semiconductor material portion by a bottom portion of the respective dummy memory film.

Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.