Patents Examined by Ng{circumflex over (a)}n V. Ng{circumflex over (o)}
  • Patent number: 6180966
    Abstract: A trench gate type semiconductor device with a current sensing cell is composed so that the orientation of crystal face at side walls of trenches forming channels of trench gates in a main cell is equal or almost equal, or equivalent or almost equivalent to the orientation of crystal face at side walls of trenches forming channels of trench gates in a current sensing cell, which brings the same performance to the main and sense cells, whereby the high accuracy current sensing can be realized.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: January 30, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Kohno, Naoki Sakurai, Mutsuhiro Mori
  • Patent number: 6180985
    Abstract: A SOI device, comprising: a SOI wafer having a stack structure of a silicon substrate, a buried oxide layer having a first and a second contact holes and a silicon layer; an isolation layer formed in the silicon layer to define a device formation region; a transistor including a gate formed over the device formation region of the silicon layer defined by the isolation layer, source and drain regions formed at the both side of the gate in the device formation region, and a channel region which is a portion of the device formation region between the source and drain region; a conduction layer being contacted with the buried oxide layer; an impurity region for well pick-up formed in the silicon layer to be contacted with the buried oxide layer; a first contact layer formed within the first contact hole of the buried oxide layer to electrically connect the channel region of the transistor and the conduction layer; and a second contact layer formed with the second contact hole of the buried oxide layer to electri
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: January 30, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: In Seok Yeo
  • Patent number: 6177706
    Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atoms currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anistropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: January 23, 2001
    Assignees: Mega Chips Corporation, Crystal Device Corporation
    Inventors: Masahiro Shindo, Daisuke Kosaka, Tetsuo Hikawa, Akira Takata, Yukihiro Ukai, Takashi Sawada, Toshifumi Asakawa
  • Patent number: 6175125
    Abstract: A wafer for testing a manufacturing process for vias has a large number of vias (millions) formed into strings that have an open circuit resistance if the string contains a defective via and have a resistance of a few thousand ohms if the string is good. A multiplexor circuit is formed on the test wafer and scans the via strings and produces a binary output denoting that the addressed string is good or defective. The addresses are generated off the wafer by a compute and a defective string is readily identified.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: January 16, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chaochieh Tsai
  • Patent number: 6175126
    Abstract: A charged coupled device is disclosed including an asymmetrical split with independent control over the regions on opposite sides of the split. The charge coupled device is configurable for use in multiline or kinetic spectroscopy, and includes two separate horizontal registers with optional charge dump regions for improving efficiency.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: January 16, 2001
    Assignee: Roper Scientific, Inc.
    Inventor: John West
  • Patent number: 6175137
    Abstract: A variable resistor, a method of manufacturing the same and a voltage bias circuit that incorporates at least one variable resistor. In one embodiment, the variable resistor includes: (1) a substrate including a doped region having an inherent resistance, (2) a controllable switch formed in the substrate, electrically coupled to the doped region and having a control terminal and (3) a controller, coupled to the control terminal, that toggles the controllable switch to modify a current flow through the doped region and thereby vary a resistance of the variable resistor.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: January 16, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Rogelio Pe{acute over (o)}n, Maarten Visee
  • Patent number: 6172410
    Abstract: A collective substrate of active-matrix substrates is divided into a first block and a second block. In cells of the first block and the second block, from a corresponding signal input pad group, an inspection scanning signal is inputted via a scanning-line short ring connecting line to scanning lines, an inspection display signal is inputted via a signal-line short ring connecting line to signal lines, and an auxiliary capacity wire signal is inputted via an auxiliary capacity wire main wire connecting line to auxiliary capacity wires. This arrangement makes it possible to perform an electrical inspection with high accuracy and efficiency on a large-format active-matrix substrate, and to manufacture an inspection probe frame in a simple manner at low cost.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: January 9, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hisashi Nagata, Mikio Katayama, Toshihiro Yamashita, Manabu Takahama
  • Patent number: 6169317
    Abstract: To make the thickness of an interlevel insulating film uniform and suppress variations in output signal, in a photoelectric conversion element including a plurality of photoelectric conversion portions, and light-shielding units having openings formed above the photoelectric conversion portions, the light-shielding units have first light-shielding layers, and second light-shielding layers formed on the first light-shielding layers via an interlevel insulating film. The first light-shielding layers have gaps (GP) for allowing two adjacent openings (OP) to communicate with each other. The second light-shielding layers have light-shielding portions (12a) above the gaps of the first light-shielding layers.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: January 2, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koji Sawada, Hiraku Kozuka, Shigeru Nishimura
  • Patent number: 6169293
    Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: January 2, 2001
    Assignee: Semiconductor Energy Labs
    Inventor: Shunpei Yamazaki