Abstract: A thin film transistor having a source region and a drain region having a low melting point region composed of a semiconductor with a melting point lower than that of the semiconductor of the channel region is provided. In the thin film transistor, the dopant concentrations of the low melting point region of the source region adjacent to the channel region and the low melting point region of the drain region adjacent to the channel region are precisely controlled. Using the thin film transistor, a high performance thin film transistor array substrate is also provided, as well as a high display speed liquid crystal display device and a high display speed electroluminescent display device having a high aperture ratio or a high pixel resolution.
Type:
Grant
Filed:
August 2, 2001
Date of Patent:
November 12, 2002
Assignee:
Matsushita Electric Industrial Co., Ltd.