Abstract: A semiconductor light emitting device according to an embodiment includes a stacked body. The stacked body includes a first semiconductor layer of a first conductivity type, a light emitting layer is provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type provided on the light emitting layer. The stacked body includes a first protrusion on an upper surface of the stacked body. The first protrusion protrudes in a first direction from the first semiconductor layer to the light emitting layer. Length of the first protrusion in a second direction perpendicular to the first direction decreases toward the first direction. The first protrusion includes a first portion and a second portion. The first portion has a first side surface inclined with respect to the first direction. The second portion is provided below the first portion and having a second side surface inclined with respect to the first direction.

Abstract: An interconnection structure includes a non-insulator structure, a dielectric structure, and a conductive structure. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The trench opening has a bottom surface and at least one recess in the bottom surface. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The conductive structure is at least separated from the bottom of the recess.

Abstract: Disclosed is a display device comprising: a substrate comprising an active region and a non-active region; a light emitting device that emits light in the active area of the substrate; a touch sensor in the active area of the substrate that senses touch of the display device, the touch sensor including a plurality of conductive layers arranged in a stacking sequence; and a plurality of routing lines in the non-active region of the substrate that are connected to the touch sensor, each of the plurality of routing lines including a plurality of routing layers, each of the plurality of routing layers made of a same material as a corresponding one of the plurality of conductive layers included in the touch sensor, and the plurality of routing layers arranged in a same stacking sequence as the stacking sequence of the plurality of conductive layers of the touch sensor.

Abstract: A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

Abstract: A liquid crystal display device includes a base unit, a gate line disposed on the base unit, a data line disposed on the base unit and crossing the gate line while being insulated from the gate line, a shielding electrode disposed on the data line and overlapping the data line and isolated from the pixel electrode and a conductive bar, the conductive bar disposed on the same layer as that on which the shielding electrode is disposed, isolated from the shielding electrode, and extending in parallel to the data line.

Abstract: Solid-state lighting devices, for example, light-emitting diodes (LEDs), which include a primary light-extraction face and a secondary light-extraction face that generally opposes the primary light-extraction face are disclosed. In some embodiments, mirrors internal to the LED may be omitted, and omnidirectional light from the active region is allowed to freely exit the primary light-extraction face and the secondary light-extraction face. In other embodiments, the first light-extraction face and second light-extraction face include opposing sidewalls of an LED. In such embodiments, mirrors internal to the LED may be utilized to direct omnidirectional light from the active region toward the first light-extraction face and the second light-extraction face.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

Abstract: A method of manufacturing a semiconductor device includes: receiving a semiconductor structure, the semiconductor structure including: a fin structure; a dummy gate across over the fin structure to define a channel region of the fin structure; and a dummy dielectric layer separating the channel region of the fin structure from the dummy gate; removing the dummy gate and the dummy dielectric layer to expose the channel region of the fin structure; and forming a doped interfacial layer covering the channel region of the fin structure, in which the doped interfacial layer includes a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.

Abstract: A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of InXAlYGa1?X?YN (0?X, 0?Y, X+Y<1).

Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.

Abstract: A light-emitting diode device includes a substrate; a plurality of light-emitting units formed on the substrate, wherein the plurality of light-emitting units form a serially-connected array, and the serially-connected array includes: a plurality of adjacent light-emitting unit columns; a first light-emitting unit row; a second light-emitting unit row; and a third light-emitting unit row adjacent with the second light-emitting unit row; and a plurality of conductive connecting structures connecting the plurality of light-emitting units; wherein the light-emitting units in the first light-emitting unit rows having the same connecting direction; wherein the second and the third light-emitting unit rows include N light-emitting units with (N?1) times of sequentially connecting via (N?1) conductive connecting structures, and the (N?1) times of the sequentially connecting comprise (N/2) times of vertical connecting or (N/2) times of horizontal connections.

Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.

Abstract: The semiconductor structure includes a plurality of FETs disposed on a semiconductor substrate, the FETs including gates with elongated shape oriented in a first direction; a first metal layer of first metal lines disposed over the gates and oriented in a second direction perpendicular to the first direction; a second metal layer of second metal lines disposed over the first metal layer and oriented in the first direction; and a third metal layer of third metal lines oriented in the second direction and disposed over the second metal layer. The first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; and the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2.

Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.

Abstract: Solid-state lighting devices, for example, light-emitting diodes (LEDs), which include a primary light-extraction face and a secondary light-extraction face that generally opposes the primary light-extraction face are disclosed. In some embodiments, mirrors internal to the LED may be omitted, and omnidirectional light from the active region is allowed to freely exit the primary light-extraction face and the secondary light-extraction face. In other embodiments, the first light-extraction face and second light-extraction face include opposing sidewalls of an LED. In such embodiments, mirrors internal to the LED may be utilized to direct omnidirectional light from the active region toward the first light-extraction face and the second light-extraction face.

Abstract: A device including a plurality of interconnected concentric coplanar diodes.