Abstract: The number of mask steps used to fabricate a TFT in an AMLCD is reduced. In particular, source and drain metallizations, as well as doped and undoped semiconductor layers are patterned at the same time, and the source and drain metallizations and the doped semiconductor layer are etched in a single etching step using an insulating passivation layer as a mask to form source and drain electrodes. Manufacturing costs can be reduced and the manufacturing yield can be improved.

Abstract: A quantum box structure and a carrier conductivity modulating quantum device are disclosed. The quantum box structure comprises a quantum boxes array including a plurality of quantum boxes arranged adjacent to each other on a common plane. Each quantum box is asymmetric in a direction orthogonal to the plane in one of composition of materials constituting the quantum box and geometry of the quantum box. The carrier conductivity modulating quantum device comprises a plurality of regions including quantum boxes arrays including a plurality of quantum boxes arranged on a common plane. Each regions exhibits at least one of a metal phase and an insulator phase. Each quantum box is asymmetric in a direction orthogonal to the plane at least in one of composition of materials constituting the quantum box and geometry of the quantum box.

Abstract: A semiconductor device has a contact plug made of a material other than tungsten, i.e., Ti and TiN films, and an interconnection pattern made of sputtered tungsten and connected to a silicon substrate through the contact plug. The tungsten film has mainly (200) and (211) orientations on the top of the insulator film to reduce the resistivity of the tungsten and has mainly (110) orientation on the exposed regions of the Ti and TiN films at the top of the contact plug.

Abstract: To provide a semiconductor device restraining high frequency impedance and restraining deterioration of a semiconductor layer, a gate wiring 26 is extended while meandering and intersects with a substantially straight line portion of a semiconductor layer 02 by a plurality of times thereby providing a plurality of gates.

Abstract: A lateral MOS transistor is described, in particular, though not exclusively, a transistor of the lateral DMOS type, in which the drain is provided with a weakly doped drain extension (8) to increase the breakdown voltage. This drain extension is also present at the ends of the drain digits, so that the "hard" drain (5) does not continue up to the edge (7) of the active region (6), but is separated therefrom by an interposed region. These regions do not contribute to the transistor effect. To reduce parasitic input capacitances, which correspond to these non-active regions, the gate poly (9) is provided in the active portion of the transistor only and is replaced in the non-active portions by poly (22) which is connected through to the source (4, 16). This poly acts as a gate which is permanently at 0 V, so that leakage currents in the non-active regions are prevented.

Abstract: Junction-type field-effect transistors are disclosed exhibiting improved resistance to impact ionization. A p-type gate region is formed above an n-type channel region between an n-type drain region and an n-type source region each having a high impurity concentration. The impurity concentration in the vicinity of a point on a boundary between the channel region and the drain region is higher than the impurity concentration in the vicinity of a point on a boundary between the channel region and the source region. The impurity concentration in the channel region can increase essentially linearly or stepwise from the source region to the drain region. The pinch-off point is shifted toward the source side, and the electric field intensity in the boundary region between the channel region and the drain region is relatively low to inhibit impact ionization.

Abstract: An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. Each photo sensor includes an individual pixel electrode. An I-layer is formed over all of the pixel electrodes. A transparent electrode is formed over the I-layer. An inner surface of the transparent electrode is electrically connected to the I-layer and the interconnect structure.

Abstract: In a charge coupled device, trap levels formed by insulating layers or floating electrodes are formed on a semiconductor layer or a semiconductor substrate. Stationary charges are trapped in some of the trap levels or floating electrodes. The charge transfer electrodes are in self-alignment with potential barrier regions.

Abstract: Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

Abstract: A first silicon oxide film, silicon nitride film, and polycrystalline silicon film are formed on the entire surface of a semiconductor substrate. Then, the polycrystalline silicon film is etched to form a first transfer electrode and then, the surface of the first transfer electrode is thermally oxidized to form a second silicon oxide film. Thereafter, a polycrystalline silicon film and a third silicon oxide film are formed on the entire surface and patterned to form a second transfer electrode. A fourth silicon oxide film is formed on the entire surface, and is etched back. Thereafter, the side wall surfaces of the third silicon oxide film and the second transfer electrode are covered with a fourth silicon oxide film. Thereafter, a light shielding film is selectively formed on them.

Abstract: A bottom-gate-type semiconductor device comprising crystalline semiconductor layers, in which the source/drain regions each have a laminate structure comprising a first conductive layer (n.sup.+ layer), a second conductive layer (n.sup.- layer) of which the resistance is higher than that of the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i-layer). In this, the n.sup.- layer functions as an LDD region, and the i-layer functions as an in-plane offset region. The semiconductor device has high reliability and high reproducibility, and is produced in a simple process favorable to mass-production.

Abstract: In order to avoid thermal runaway bipolar transistors, emitters are provided with ballast resistors. Elongate ballast resistors may be used, part of the lengths being connected for obtaining suitable resistance and design variability. The emitters are split up into a plurality of emitter portions, each with a separate emitter ballast resistor. The collector and base are correspondingly split up. The transistor is split up into unit cells, each comprising an emitter, a ballast resistor, a base, and a collector, which are respectively connected via respective common leads. This structure may advantageously be realized in a SOI technique, the galvanic isolation enabling unproblematic mixing of digital and analog and power devices in the same chip.

Abstract: A field controlled bipolar switch having a bulk single crystal silicon carbide substrate of a first conductivity type having an upper surface and a lower surface. A first epitaxial layer of a second conductivity type silicon carbide is formed upon the upper surface of the substrate. A second epitaxial layer of the second conductivity type silicon carbide is formed on the first epitaxial layer of silicon carbide. A plurality of regions of a third conductivity type silicon carbide are formed in the second epitaxial layer to form a gate grid in the second epitaxial layer. A third epitaxial layer of the second conductivity type silicon carbide is formed on the second epitaxial layer and a fourth epitaxial layer of the second conductivity type silicon carbide is formed upon the third epitaxial layer. The fourth epitaxial layer has a higher carrier concentration than is present in the first, second and third epitaxial layers.

Abstract: A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate, in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Abstract: A charge coupled device of buried channel type suitable to drive the device by clock pluses having a low voltage is disclosed. Channels of the charge coupled device comprises first to third regions. The first region has a first impurity concentration. The second region has a second impurity concentration lower than the first impurity concentration. The third region has a third impurity concentration lower than the second impurity concentration. A first transfer electrode is formed on the first region. A second transfer electrode is formed on the second region.

Abstract: A p-type well and an n-type well surrounding the p-type well are formed in a p-type semiconductor substrate under a field insulating film. A polysilicon resistance film is formed on the field insulating film simultaneously with a floating gate formed in a memory cell region. A polycide conductive film is formed on a interlayer insulating film simultaneously with an auxiliary bit line formed in the memory cell region, and the polycide conductive film is connected to the resistance film by a contact formed in a via hole. A wiring line formed on an interlayer insulating film is connected to the polycide conductive film by a contact formed in a via hole penetrating the interlayer insulating film. The two via holes are formed at positions corresponding to regions in the p-type well. A negative voltage is applied to the wiring line, and the potential of a predetermined point on the resistance film is measured.

Abstract: A packaging solution for CCD devices and other opto-electronic applications that offers a lower cost, automated assembly process. A package made of a moldable plastic material with low moisture permeability, and high dimensional stability by employing materials such as liquid crystal polymer. While relatively high cost plastic materials may be used, the overall cost is expected to be substantially lower than a corresponding ceramic package. An interconnect circuit pattern is then be formed on the plastic using one of a variety of plating options known in the circuit board, and in the molded interconnect industry. The ability to mold a flexible circuits into the package results from the use of these materials. Conductors of standard materials in the circuit board industry; e.g., copper with selective nickel and gold plating are employed on a non reflective substrate surface. The CCD sensor is mounted to this plastic substrate and connected to the conductive pattern using standard wire bonding processes.

Abstract: A solid state microstructure comprises a substrate (10,50,80), a detector element extending outwardly from a surface of the substrate and having first (14,60,88) and second (16,64,90) electrodes on opposing sides thereof, the detector element incorporating an onboard optoelectrically-triggered gating structure. Gating may be achieved by flooding a specified area of the detector element with gating light, preferably from a laser, thereby causing that region to become conductive.

Abstract: The present invention relates to a method for connecting the two conductive lines located on separate layers with an intervening insulation layer between them, and a wiring structure formed by the same method. The method includes the steps of forming a first conductive layer on the substrate, forming an insulation layer on the first conductive layer, forming a second conductive layer having a first portion overlapping the first conductive layer, removing a portion of the first portion of the second conductive layer that overlaps the first conductive layer to form a top contact hole exposing a portion of the insulation layer, removing the exposed portion of the insulation layer through the top contact hole to form an enlarged contact hole, and forming a conductive pad in contact with the first conductive layer and the second conductive layer through the enlarged contact hole.

Abstract: In a solid-state image sensor, first color filters for a first color and associated photodiodes are disposed with a uniform pitch in all pixels in a chip. As to microlenses, however, those in pixels located in a central area of the chip are disposed to substantially align with aperture centers of the pixels, and those in pixels distant from the center of the chip are disposed to shift their centers from aperture centers of the pixels by first shift amounts (offset amounts) in a direction toward the chip center or chip peripheries. The first shift amounts are determined, depending on the wavelength of the first color, to increase in a predetermined rate from the chip center toward the chip ends. Second shift amounts for shifting microlenses in pixels for a second color are determined to increase from the chip center toward the chip ends in a rate different from the rate of the first shift amounts accounting the wavelength of the first color.