Patents Examined by Ngann V. Ngo
  • Patent number: 5747829
    Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: May 5, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Yoshitaka Sugawara