Abstract: Each logical stripe is subjected to a judgment whether or not it should be selected as object of repack (rearrangement) by referring to an address conversion table. For the judgment, &agr; representing the percentage of valid logical block numbers and &bgr; representing the percentage of the consecutive logical address numbers of adjacently located logical blocks are computationally determined. Each logical stripe that satisfies the requirement that “&agr; is not smaller than a predetermined value A and &bgr; is not greater than a predetermined value B” is subjected to a repack processing operation. As a result, logical stripes whose valid blocks are physically distributed can be subjected to a repack processing operation with priority.

Abstract: An improved mechanism for managing an object cache is disclosed. An object cache manager receives a request for an object resident in an object cache. A determination is made as to whether the requested object is currently within a particular portion of the object cache. If the requested object is within this particular portion, then the object cache manager keeps the requested object within this portion of the cache by maintaining the requested object at its current position relative to other objects in the object cache. By removing the overhead of repositioning objects within a particular portion of the object cache, the efficiency of object cache management is significantly improved.

Abstract: Providing high availability cache coherency in a distributed cache environment for a storage cluster. An extent owner node in a cluster controls extent disk requests and the locking and demotion of extent data. An extent client node may access the data but does not control destaging or locking. The extent client waits for a lock state grant prior to completing any I/O request. An extent client is allowed to receive data from a host for a write request and later let the extent owner sort out the proper cache coherency order. An extent client is not required to request a lock state change from the extent owner when a read cache hit occurs in the extent client. When a read miss occurs in an extent client, the extent client can initiate a stage request from disk and request the owner for a lock state change at a later time.

Abstract: A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the pipeline. Tag allocation logic compares the last store address with the store address of a new store and allocates the same tag as was previously allocated to the last store if the addresses are in the same cache line, and assigns the next incremental tag otherwise. Tag registers store write buffer tags associated with store data in write buffers waiting to be written to memory on the processor bus. When the new store reaches the write buffer stage, tag comparators compare the new store tag with the write buffer store tags. If the tags match, the write buffer control logic combines the new store data with the store data in the write buffer with the matching tag.

Abstract: A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.

Abstract: A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.

Abstract: A microprocessor is equipped with an address translation mechanism for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer, and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic for controlling the operation of the address translation buffer. The address translation buffer includes a lower-level buffer organized as a lower-level hierarchy of the address translation buffer and having no entry lock function, and a higher-level buffer organized as a higher-level hierarchy of the address translation buffer and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer.

Abstract: A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized.

Abstract: A method for adaptively selecting an optimal pre-fetch policy between a first pre-fetch policy, in which a request for desired data from a data-set is satisfied by reading the desired data, and a second pre-fetch policy, in which a request for desired data from a data-set is satisfied by reading the data-set. The method includes collecting statistics on a number of avoidable read-misses. On the basis of the statistics, a first threshold value is defined and frequently updated. Upon detection of an unavoidable read-miss, a random number is generated and the optimal pre-fetch policy is selected on the basis of a sign of a difference between the threshold value and the random number.

Abstract: An address and data transfer circuit includes enable circuit for enabling a single-port memory in accordance with an access requirement from a corresponding port out of a plurality of external ports. An active address selecting circuit selects an address from the corresponding port and transfers the address to the single port memory responsive to activation of the enabling circuit. An active data selecting circuit selects a data from the corresponding port and transfers the data to or from the single port memory, responsive to activation of the enabling circuit.

Abstract: According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.

Abstract: A method for transmitting a data of a disk recording medium including: a first step of reading file management information for managing a data recorded in a file structure in a disk recording medium; a second of storing the read file management information in a storing unit different to the recording medium; and a third step of reading and transmitting a corresponding file management information as stored in the storing unit when the file management information is requested. By doing that, the file management information that is frequently requested to be transferred, such as a file system data managing a data in a file structure recorded in a disk recording medium such as a CD-ROM, is stored in a specific storing area so as to be quickly read and transmitted to a connected instrument such as a personal computer, without performing a tracking servo operation to drive a sled motor. Thus, the transfer rate of the optical disk driver such as the CD-ROM can be highly improved.