Abstract: The PWM modulation circuit according to the invention is connected to an input terminal for an analog baseband signal and a staircase generating circuit generating a staircase wave, and carries out PWM modulation to a staircase wave input from the staircase generating circuit based on an analog baseband signal input from the input terminal. The staircase generating circuit includes a plurality of constant current source circuits, a plurality of switches connected to the plurality of constant current source circuits on a one-to-one basis, a serial-parallel conversion circuit that carries out serial-parallel conversion to a clock signal input from a clock signal input terminal and outputs the result to the plurality of switches, and an output voltage control circuit that converts a constant current input from the plurality of constant current source circuits into a constant voltage at an arbitrary value and outputs the result.

Abstract: The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC's parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.

Abstract: A device for activating a control unit is proposed. It includes at least one operating element operable by a user as well as analog encoding means assigned to the operating element. To generate an activation signal for a control unit, deactivation means are provided that deactivate at least one analog encoding means in order to digitally encode the operating element.

Abstract: A method, device and computer program for handling a data stream comprising a number of data objects, wherein for at least one of these data objects a decision is made whether a compression is conducted based on a value representing a compression factor of the data object.

Abstract: A compression method and apparatus identifying candidates for compression by selectively fingerprinting shingles or overlapping subsets of an input dataset and creating a set of characteristic input fingerprints based on fingerprint value. In some cases, the characteristic fingerprints are selected based on the relative value of the fingerprints with respect to other fingerprints in the same cluster. Potential matches may be identified and confirmed by comparing the characteristic input fingerprints with fingerprints associated with a history. Advantageously, some examples according to the current invention may be applied to input data such as: data, files, bit streams, byte streams, packet streams and previously encoded, compressed and/or encrypted data.

Abstract: A technique for constructing a dictionary word list for use in a data compressor is provided by determining a set of words that are included in the dictionary word list and sorting each subset of words having a common starting character by lengths of the words. Partitions are formed and identified based on the common starting character and word length, with each partition being stored in memory and indexed.

Abstract: A hardware accelerator for improving the decompression performance when decompressing data in Lempel-Ziv-Huffman compressed data format. The use of a Huffman encoding second stage in the popular and widely-used Lempel-Ziv-Huffman standard improves the compression ratio but complicates the decompression, because the Huffman encoding is applied selectively only to certain pails of the Lempel-Ziv tokens, and thus Huffman decoding must also be applied selectively during decompression. The present invention features a variable-length token decoder which is able to selectively decode the Huffman-encoded portions of the compressed data, and therefore enables high-performance decompression for compressed data having a very good compression ratio. Such an accelerator is well-suited for use in data processors which are to be loaded with pre-compressed data and software applications, particularly those employing flash memory.

Abstract: A SAW filter includes a plurality of IDTs arranged on substrate along a SAW propagation direction, and balanced signal terminals connected to an IDT. The SAW filter is a floating balanced type. The plurality of IDTs are arranged so as to provide a horizontally asymmetrical structure with respect to an imaginary axis that is positioned at the approximate center of the center IDT in the SAW propagation direction and which is substantially perpendicular to the SAW propagation direction. Thus, a SAW filter having filtering characteristics and a balance-to-unbalance conversion function is achieved with high balance between the balanced signal terminals.

Abstract: A power amplifier module is provided with a function of protecting an amplifying device against destruction caused by a standing wave by reflection from an antenna end in load variation. Increase in base current from idling current of a final stage amplifying portion GaAs-HBT in load variation is detected and canceled and collector current is restrained to thereby prevent an increase in output and prevent destruction of GaAs-RET. By also using a function of successively lowering idling current when power source voltage is elevated and a clipping function of diodes connected in parallel with output stage GaAs-RET, voltage as well as current more than necessary are avoided from being applied on the output stage GaAs-RET.

Abstract: An electronic device having a current switch type driver is provided. The current switch type driver includes a differential circuit that supplies a current to a transmission channel according to a signal. In the electronic device, a signal wire that transmits the signal to the differential circuit has a transmission channel structure.

Abstract: A method of lossless data compression is provided which uses a grammar transform to sequentially construct a sequence of irreducible context-free grammars from which an original data sequence can be recovered incrementally. The data sequence is encoded using any one of a sequential encoding method, an improved sequential encoding method and a hierarchical encoding method.

Abstract: Disclosed is a dual band coupler, in which a dielectric layer having a coupling signal line is positioned between dielectric layers having a first main signal line and a second main signal line. Coupling coefficients of first and second signal lines can be independently controlled by laminating different numbers of dielectric layers between the coupling signal line and main signal lines, respectively. A shielding pattern for excluding mutual electromagnetic interference between the first and second main signal lines is formed on the dielectric layer having the coupling signal line to improve an isolation, and a small sized-dual band coupler can be provided because the dielectric layer having a ground pattern can be omitted.

Abstract: The present invention relates to an analog/digital converter including an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit. The digital conversion unit has digital-value storage registers, which are each provided for one of the stages. Each of the register is used for storing a digital value completing error correction for each segment, and adapted to output the digital value that corresponds to a segment number. The digital conversion unit also has an error-computation control unit, which controls the stages so that a specific one of the stages, inputs an error computation analog signal. The error-computation control unit then computes an error of the specific stage on the basis of digital-converted data computed from the digital values corresponding to segment numbers received from all the stages following the specific stage.

Abstract: An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corresponding to a multiplied value of the phase shift signal and the oscillation signal, and an error signal generator outputs an error signal according to the multiplied signal. The output frequency of the oscillator is controlled according to the error signal.

Abstract: An operational amplifier for a pipeline analog-to-digital converter (ADC). The operational amplifier includes a cascaded chain of differential amplifiers, each differential amplifier including resistive-averaged common mode feedback to produce a common mode voltage for the differential amplifier, a particular differential amplifier of the chain having the highest gain of the gains of the differential amplifiers. The operational amplifier has one or more feedback paths each including a compensation capacitor to compensate the operational amplifier.

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Abstract: A power line communications apparatus and method for providing communications over power leads connecting two pieces of electrical equipment. One power lead is split into similarly sized first and second parallel conductors. The first and second conductors pass through a current transformer, the first conductor having a load current flow opposite the second conductor with respect to the current transformer. The transmitted communications signal is applied to the secondary of the current transformer and is induced on the primary of the transformer, namely a loop formed by the first and second conductors. A second current transformer serves as a receiving transducer and senses the communications signal on the first and second conductors.

Abstract: A differential transimpedance amplifier includes a differential transconductance stage to provide a current to a differential transimpedance stage. The differential transimpedance stage includes two gain stages and provides a voltage. A first feedback element is coupled in parallel with the differential transimpedance stage.

Abstract: A mixed signal processing unit with non-linear feedforward paths to improve total harmonic distortion (THD) and noise characteristics of the processor. Specifically the signal processing unit includes a first integrator stage configured to receive an input signal and configured to generate a first integrated signal in response thereto, a second integrator stage coupled to the first integrator stage and configured to generate a second integrated signal from the first integrated signal, a sampling stage coupled to the second integrator stage and configured to sample the second integrated signal received from the second integrator stage at a sample frequency and to generated a logic signal, and a non-linear feed-forward signal path coupled between the first integrator stage and the sampling stage.

Abstract: A method for digital-to-analog conversion of a digital signal (xd(ti)) comprises resolving the signal (xd(ti)) in the time region into intervals and successively transforming these intervals on the basis of orthogonal functions (gjd(t)). Coefficients (ajd) associated with the orthogonal functions (gjd(t)) are determined and converted from digital to analog and the signal (xa(t)) is transformed back in the analog region on the basis of analog coefficients (aj), which result therefrom, by means of orthogonal functions (hj(t)).