Abstract: The method of the current invention provides a fault tolerant access to a network resource. A replicated network directory database operates in conjunction with server resident processes to remap a network resource in the event of a server failure. The records/objects in the replicated database contain for each network resource, a primary and a secondary server affiliation. Initially, all users access a network resource through the server identified in the replicated database as being the primary server for the network resource. When server resident processes detect a failure of the primary server, the replicated database is updated to reflect the failure of the primary server, and to change the affiliation of the network resource from its primary to its backup server. This remapping occurs transparently to whichever user/client is accessing the network resource.

Abstract: Disclosed is a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD), a random access memory (RAM), and a LAN controller. A flash memory module is coupled to the CPU and an input/output (IO) bus and includes a basic input output system (BIOS) stored therein. The BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The BIOS is further operative on completion of the POST for transferring a portion of BIOS from the module to the RAM and for transferring control of the of the computer system to the BIOS portion. The portion of BIOS is operative to load a protected mode operating system (OS) into RAM and transfer control to the OS. The system further includes a logic circuit coupled to the flash memory module and the IO bus.

Abstract: A compressor driving apparatus comprises a module including a power supply, an inverter for driving a compressor, an inverter driver for driving the inverter, a CPU for generating a signal to be used for driving the inverter and having a function for communicating with outside, a storage circuit for storing data which is alterable from an external device, and a relay driver for driving an external relay. The inverter and other circuit components are disposed within the module such that they are thermally separate such that an inverter driving signal from the CPU is transferred accurately to the inverter and that a power supply having an output voltage with low distortion is realized, thereby improving the operating efficiency of the compressor. Because the storage circuit and the power supply circuit are built-in, standardization of the compressor driving apparatus is easily realized.

Abstract: A plurality of application servers, a client, an integrated authentication server and a security information management server are connected to a network. A user having different combinations of user ID's and passwords or certificates for a plurality of kinds of services processed by the plurality of application servers makes requests for services to the individual application servers through the client by using a common integrated certificate. An application server receiving the integrated certificate from the client transfers it to the integrated authentication server. The integrated authentication server checks information of the security information management server to decide whether the right of the user to access the service is valid and when valid, transmits to the application server a combination of a user ID of the user and a password or a certificate concerning the service.

Abstract: A computer system is implemented according to the invention when an computer process interactively allows a user to configure a computer system. The device according to the present invention abstracts functionality common to all application specific computer configuration problems and locates it in a single framework. In this way, multiple application specific configuration processes can be developed easily without duplicating the work of creating common features.

Abstract: The present invention relates to a network unauthorized access analysis method, a network unauthorized access analysis apparatus utilizing this method and a computer-readable recording medium having a network unauthorized access analysis program recorded thereon, and is capable of processing arbitrary data, performing arbitrary communication between networks, easily dealing with an increase in a number of protocols and coping with arbitrary protocols.

Abstract: A method and system for remotely troubleshooting a local computer connected to an array of local peripheral devices include a data collector connected to the local computer. The data collector includes a signal interceptor for intercepting signaling information transmitted by the computer to the peripheral devices. The intercepted signaling information has been formatted for processing by the local peripheral devices at a point of interception. The data collector further includes a transceiver having a transceiver input configured to relay signaling information received from remote peripheral devices located at a remote troubleshooting site to input/output (I/O) ports of local peripheral devices. A transceiver output is configured to transmit intercepted signaling information to the remote peripheral devices at the remote troubleshooting site.

Abstract: A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories.

Abstract: An in-circuit emulator (ICE) including an internal trace memory and a bit-width converter. The internal trace memory is embedded in an ICE CPU to trace CPU internal signals fed from a CPU core that executes the same operations as a CPU of a debugged system. The bit-width converter converts the CPU internal signal, which is read out of the internal trace memory, into a plurality of reduced bit-width signals, and supplies them to an ICE controller outside the chip of the ICE CPU in multiple cycles. The configuration makes it possible to remove the restriction imposed, by the number of terminals of the ICE CPU chip, on the number of bits of the CPU internal signal to be output in parallel, and to overcome the difficulty involved in sampling the internal CPU signals by the trace memory, even if the operation frequency of the ICE CPU increases.

Abstract: Code is written to a selected portion of a nonvolatile memory having a first portion associated with a first range of addresses and a second portion associated with a second range of addresses, wherein the selected portion is the second portion. Toggling a block selector swaps addresses of the first and second portions, wherein the first range of addresses reference the second portion of nonvolatile memory and the second range of addresses reference the first portion of nonvolatile memory. An apparatus includes a processor that initiates a boot sequence at a pre-determined address. An address decoder accesses a one of a first and a second block of nonvolatile memory in response to the pre-determined address in accordance with a value of the block selector. A method using a group selector includes the step of receiving an address from a processor. The address is decoded to access one of a first and a second group of blocks of nonvolatile memory in accordance with a value of the group selector.

Abstract: In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

Abstract: A computer system includes system memory, containing BIOS instructions, having multiple bootable partitions and the ability to enable Automatic System Recovery (ASR) protection during an early phase of the boot process. Early ASR allows errors occurring during the boot process to be handled by established ASR techniques. Multiple BIOS partitions allows a user to upgrade and/or test new system routines without the potential of losing the functionality of their existing system.

Abstract: An access control processor provides for display of a message related to an authorization status of an information receiver in a conditional access system for receiving an information segment when the information segment is provided separately by each of a plurality of different service providers. The processor processes a plurality of authorization signals respectively related to the information segment provided separately by the plurality of different service providers; determines which of a plurality of different possible authorization statuses is applicable for the received information segment for each of the respective authorization signals related to the different service providers; selects one of the determined statuses in accordance with a predetermined priority; selects from a plurality of different possible authorization status messages the message applicable to the status determined in accordance with said priority; and provides the selected message for display.

Abstract: A technique for authenticating a headerless-ID magnetic disk includes the steps of inserting the headerless-ID magnetic disk having a plurality of defective locations and an encrypted defect map into a removable drive unit, retrieving the encrypted defect map from the magnetic disk, storing the encrypted defect map into a memory in the removable drive unit, decrypting the encrypted defect map to form a defect map identifying the plurality of defective locations, and using the defect map in the memory to provide access to locations on the headerless-ID magnetic disk other than the plurality of defective locations.

Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a shifter configured to selectively shift the bit pattern; a data output operable to output the bit pattern; and a sign extension operator coupled with the data output and operable to provide a sign extension signal thereto. The present invention additionally discloses a barrel shifter and a method for manipulating a bit pattern.

Abstract: An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.

Abstract: A device driver initiates a DMA transfer and repeatedly reads a semaphore from a specified location in system memory. Upon completion of a DMA transfer, a DMA controller writes a semaphore containing status information to the specified location in system memory, informing the device driver that the DMA transfer is completed. A cache memory for the specified location in system memory is provided to further reduce the latency between DMA transfers.