Abstract: A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Abstract: A method for formation of openings in semiconducting devices not limited by constraints of photolithography include forming a first dielectric layer over a semiconducting substrate, depositing a polysilicon layer over the first dielectric layer, forming a second dielectric layer over the polysilicon layer, forming a third dielectric layer over the second dielectric layer, etching a dielectric window through the third dielectric layer, forming a fourth dielectric layer into the dielectric window and over the third dielectric layer, the fourth dielectric layer being of a material dissimilar to the second dielectric layer, etching the fourth dielectric layer anisotropically using an etchant with a high selectivity ratio between the fourth dielectric layer and the second dielectric layer thereby forming a spacer, and etching portions of the first and second dielectric layers and the polysilicon layer anisotropically, the portions underlying an area bounded by a periphery of the spacer thereby forming the opening.

Abstract: To form a bottom electrode of a capacitor of a semiconductor device, a first insulation layer pattern having a first contact hole is formed on a substrate, and a contact plug for the bottom electrode is formed in the contact hole. A second insulation layer is formed on the first insulation layer pattern and the contact plug. The second insulation layer has a second etching rate higher than a first etching rate of the first insulation layer pattern. The second insulation layer is etched to form a second insulation layer pattern having a second a contact hole exposing the contact plug. A conductive film is formed on the sidewall and the bottom face of the second contact hole. According to the difference between the first etching rate and the second etching rate, the etching of the first insulation layer pattern near the contact plug is reduced.