Abstract: A geometric diode, method and device applications are described. The geometric diode is produced including a device body formed from an electrically conductive material having an equilibrium mobile charge density, and having a device surface configuration. The material has a charge carrier mean free path with a mean free path length and the device body size is selected based on said the free path length to serve as an electrically conductive path between first and second electrodes delimited by the device surface configuration that is asymmetric with respect to a forward flow of current in a forward direction from the first electrode to the second electrode as compared to a reverse current flow in an reverse direction from the second electrode to the first electrode. A system includes an antenna for receiving electromagnetic radiation coupled with the geometric diode antenna to receive the electromagnetic radiation to produce an electrical response.

Abstract: A method for manufacturing a heterostructure for applications in the fields of electronics, photovoltaics, optics or optoelectronics, by implanting atomic species in a donor substrate so as to form an embrittlement area therein, assembling a receiver substrate on the donor substrate, wherein the receiver substrate has a larger thermal expansion coefficient than that of the donor substrate, detaching a rear portion of the donor substrate along the embrittlement area so as to transfer a thin layer of interest of the donor substrate onto the receiver substrate, and applying a detachment annealing after assembling and but before detaching, in order to facilitate the detaching. The detachment annealing includes the simultaneous application of a first temperature to the donor substrate and a second temperature different from the first to the receiver substrate; with the first and second temperatures being selected to reduce the tensile stress condition of the donor substrate.

Abstract: Methods and apparatus for encapsulating organic light emitting diode (OLED) structures disposed on a substrate using a hybrid layer of material are provided. The processing parameters used during deposition of the hybrid layer of material allow control of the characteristics of the deposited hybrid layer. The hybrid layer may be deposited such that the layer has characteristics of an inorganic material in some sublayers of the hybrid layer and characteristics of an organic material in other sublayers of the hybrid layer. Use of the hybrid material allows OLED encapsulation using a single hard mask for the complete encapsulating process with low cost and without alignment issues present in conventional processes.

Abstract: A package structure of semiconductor light emitting element is provided. The package structure of semiconductor light emitting element includes a substrate, a light emitting element and a transparent conductive board. A first electrode and a second electrode are disposed on the substrate. The light emitting element is disposed on the substrate and between the first electrode and the second electrode. A first bonding pad and a second bonding pad are disposed on the light emitting element. The transparent conductive board has a first surface and a second surface opposite to the first surface. The second surface of the transparent conductive board is located over the light emitting element for electrically connecting the first electrode and the first bonding pad and electrically connecting the second electrode and the second bonding pad.

Abstract: A photo-coupler device includes a P-type substrate, a P-type epitaxial layer, an insulation layer, a plurality of shielding layers, a metal layer and a passivation layer. The P-type epitaxial layer is deposited on the P-type substrate and includes two conducting regions and a plurality of N+ electrode regions between the two conducting regions. The insulation layer is deposited on the P-type epitaxial layer. The shielding layers comprising first shielding layers and second shielding layers are deposited in the insulation layer in parallel in a horizontal direction, and the first shielding layers are arranged for correspondingly covering the two conducting regions, the second shielding layers are arranged for correspondingly covering the at least one of the N+ electrode regions. The metal layer is made of Ag and is deposited on the insulation layer. The passivation layer is deposited on the metal layer.

Abstract: A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package is configured to support a plurality of light sources. The light sources may be mounted on a mounting section of the PLCC package's lead frame and the mounting section of the lead frame may extend diagonally with respect to the housing of the lead frame.

Abstract: A semiconductor package is provided, including a laminate substrate with an aperture sized to receive a semiconductor die. Through-holes in the substrate are filled with a thermally conductive adhesive. A first heat spreader is attached to the by the adhesive, and a semiconductor die is positioned in the aperture with a back face in thermal contact with the heat spreader. Wire bonds couple the die to electrical traces on the substrate. A second heat spreader is attached by the adhesive to the substrate over the die, directly opposite the first heat spreader. A portion of the second heat spreader is encapsulated in molding compound. Openings in the second heat spreader admits molding compound to fill the space around the die between the heat spreaders. Heat is transmitted from the die to the first spreader, and thence, via the through-holes and conductive paste, to the second heat spreader.

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

Abstract: A light emitting device is provided that includes a substrate, a buffer layer disposed on an r-plane of the substrate, the buffer layer having a rock salt structured nitride, and a light emitting structure arranged on the buffer layer, the light emitting structure being grown in an a-plane.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Abstract: A resonator unit includes a resonator chamber with a first opening for receiving container in a predefined position and for heating the container with microwaves coupled into the resonator chamber. The chamber has a second opening via which the microwaves are coupled into the resonator chamber, wherein the geometry of the resonator chamber relative to the predefined position of the container in the first opening is adapted by a device for adapting the geometry so that an electric field produced in the resonator chamber in a working mode is symmetrical in relation to the container or the impedance of the resonator unit equipped with container is approximately constant for containers of different configurations.

Abstract: A method of forming a SONOS gate structure. The method includes forming a gate pattern with sidewalls on a substrate, wherein the gate pattern includes a gate dielectric layer patterned on the substrate and a gate electrode patterned on the gate dielectric layer, forming a first oxide layer on the gate pattern and the substrate; etching back the first oxide layer to expose the substrate and the top of the gate electrode, leaving oxide spacers along the sidewalls of the gate pattern respectively; forming a second oxide layer on the substrate and the oxide spacers; and forming trapping dielectric spacers on the second oxide layer adjacent to the sidewalls of the gate pattern respectively.

Abstract: An electric oven includes a box casing presenting side walls, a rear wall, an upper wall and a lower wall, an opening and a closure door for this latter, the walls bounding an oven cavity heated by heating structure functionally associated with at least one of the walls. The heating structure is arranged to heat the cavity by induction and includes a generator arranged to generate an electromagnetic field, an electrically insulating material disposed between the generator and the oven wall at which the heating structure is positioned, and magnetically insulating structure is disposed on the outside of the oven with reference to the wall, the generator, the electrically insulating structure and the magnetically insulating structure defining a single, layered structure fitted to the oven wall.

Abstract: Integrated circuits with transistors and decoupling capacitor structures are provided. A decoupling capacitor structure may include multiple deep trench structures formed in a semiconductor substrate. The deep trench structures may each be lined with high-? dielectric material. A conductive metal layer for use in controlling threshold voltages associated with n-channel or p-channel devices may be formed over the high-? dielectric liner. Conductive material such as aluminum may be used to fill the remaining trench cavity. The high-? dielectric liner may be simultaneously deposited into the deep trench structures and gate regions of the transistors. In one suitable arrangement, the deep trench structures and transistor metal gates for at least a selected type of transistors may be formed in parallel. In another suitable arrangement, the deep trench structures and the transistor metal gates may be formed in separate steps.

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract: A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

Abstract: Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.

Abstract: A method of patterning a mesoporous nano particulate layer on a conductive substrate comprises the steps of depositing a pattern on the conductive substrate, depositing a layer of titanium dioxide by atomic layer deposition on the substrate, removing the underlying pattern with a solvent to leave discrete areas of titanium dioxide, depositing a mesoporous nano particulate layer over the whole substrate, and depositing a second layer of titanium dioxide by atomic layer deposition above the mesoporous nano particulate layer whereby the areas of mesoporous nano particulate layer and second titanium dioxide layer over the areas where the first layer of titanium dioxide was removed with the solvent fall off, leaving the patterned mesoporous nano particulate layer.