Abstract: An information processing apparatus includes a conversion buffer configured to store a conversion pair of a virtual address of a page and a physical address, a page table cache configured to store data in a page table at a level other than a last level and a physical address of the data in association with each other, a memory, and a processor coupled to the memory, and configured to store a hash of the virtual address and process management information of a conversion source in each entry of the page table cache, and when executing a maintenance instruction of deleting the conversion pair in the conversion buffer by specifying at least one of the hash of the virtual address or the process management information, delete an entry of matching at least one of the hash of the virtual address and the process management information, in the page table cache.

Abstract: A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

Abstract: A software RAID/management communication system includes a chassis housing a software Redundant Array of Independent Disk (RAID) subsystem and a management subsystem that are each coupled to a storage device having a storage device memory subsystem. The software RAID subsystem provides a software RAID information request in the storage device memory subsystem that requests the management subsystem provide software RAID information associated with the operation of a software RAID provided by the software RAID subsystem, the software RAID subsystem then periodically accesses the storage device memory subsystem and, when the software RAID subsystem determines that the management subsystem has provided a software RAID information response in the storage device memory subsystem, the software RAID subsystem retrieves the software RAID information that was provided in the storage device memory subsystem by the management subsystem.

Abstract: A storage object and an associated permissions record is stored at a storage server. The permissions record indicates that some storage consumers are not permitted to perform a type of I/O operation on the storage object. In response to detecting that an event of a deletion triggering type with respect to the records, a modified version of the permissions record is stored at the server, indicating that the storage consumers remain prohibited from performing the I/O operations. In response to receiving a command to perform a particular I/O at the server after the modified version has been stored, the modified version is used to process the command.

Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

Abstract: An operating method of a storage controller includes receiving a permanent write protection command; checking a distribution of first data included in a target namespace corresponding to the permanent write protection command; setting at least one memory region as a protected memory region, based on at least one metric corresponding to each of a plurality of non-volatile memory devices; and migrating at least a portion of the first data, which is stored in a remaining memory region different from the protected memory region, to the protected memory region.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: Aspects of a storage device are provided that handle host commands associated with active and inactive zones using a hybrid L2P mapping system. The storage device includes a NVM, a controller, a first volatile memory and a second volatile memory. The controller allocates, as a superblock, one or more physical blocks respectively in one or more memory dies of the NVM, receives write commands including logical addresses associated with active zones, and stores in an L2P mapping table L2P address mappings of these logical addresses to physical addresses associated with either volatile memory or the superblock. The controller refrains from storing L2P address mappings for inactive zones, instead storing in a superblock mapping table a mapping of superblocks to inactive zones in response to respective zone finish commands. As a result, L2P mapping table sizes are reduced, zone read, reset, and TTR performance are increased, and reduced WAF is achieved.

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

Abstract: An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.

Abstract: An apparatus comprises a memory having a data cache stored therein and a control circuit operably coupled thereto. The control circuit is configured to update that data cache in accordance with a scheduled update time. In the latter regards, by one approach, the control circuit computes selected entries for the data cache prior to the scheduled update time pursuant to a prioritization scheme to provide a substitute data cache. At the scheduled update time, the control circuit switches the substitute data cache for the data cache such that data queries made subsequent to the scheduled update time access the substitute data cache and not the data cache.

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

Abstract: A data storage method and apparatus. The embodiments include receiving first data and a latency level identifier of the first data, where the latency level identifier of the first data is for indicating a requirement level of the first data for access latency; determining, based on the latency level identifier of the first data and correspondences between memory pages of different types and latency level identifiers, that a memory page corresponding to the first data is a first memory page of storage device, where the storage device includes the first memory page and a second memory page, the first memory page and the second memory page are of different types, memory pages of different types have different access latency; and storing the first data on the first memory page.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to maintain a plurality of virtual pools, wherein each virtual pool corresponds with an logical block address (LBA) range, update a counter of a virtual pool, wherein the counter corresponds to a health of the LBA range, and select, based on the counter, the virtual pool to program data to. The controller is further configured to maintain a counter for each application having data programmed to the virtual pool, where the counter is increased for each write operation to the virtual pool. When the counter equals or exceeds a threshold value, the controller is configured to send a warning to each application associated with the virtual pool having the counter that equals or exceeds the threshold value.

Abstract: Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object parameters define properties of the data flows. Data that configures the data processing array to implement the data flows among the plurality of different levels of the memory hierarchy and the external memory is generated based on the plurality of buffer objects and the buffer object parameters.

Abstract: A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit includes a threshold-tracking circuit which is configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status. In response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status.

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

Abstract: Systems and methods are disclosed including a controller and a memory device comprising a first plane and a second plane where each plane is associated with a respective queue maintained by the controller. The local media controller is configured to perform operations comprising storing, in a first queue associated with the first plane, a first plurality of memory access commands; storing, in a second queue associated with the second plane, a second plurality of memory access commands; and processing the first plurality of memory access commands from the first queue and the second plurality of memory access commands from the second queue.