Patents Examined by Nictor A Mandala
  • Patent number: 11322646
    Abstract: Some embodiments of the present disclosure provide a light-emitting diode package. The light-emitting diode package includes a transparent substrate. The light-emitting diode package also includes a first light-emitting diode which is disposed on the transparent substrate and has a first multiple quantum well structure. The light-emitting diode package further includes a second light-emitting diode which is disposed on the transparent substrate and has a second multiple quantum well structure. The first multiple quantum well structure and the second multiple quantum well structure are disposed to emit lights with different wavelengths.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: May 3, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Shun-Yuan Hu, Chin-Lung Ting, Ker-Yih Kao, Li-Wei Mao
  • Patent number: 11239096
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Patent number: 11152521
    Abstract: A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 1×1021 cm?3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 19, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Takashi Go, Takashi Ishizuka