Patents Examined by Nidra Richards
  • Flash memory process using polysilicon spacers
    Patent number: 6365455
    Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: April 2, 2002
    Assignee: Mosel Vitelic, Inc.
    Inventors: Wen-Doe Su, Thomas Chang, Kuo-Tung Sung, Mao Song Tseng, Shih-Chi Lai, Kun-Yu Sung, Liang-Chen Lin