Abstract: A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element, thereby creating a full mesh network. The full mesh network is located on a processor card, multiples of which may be grouped in a shelf having a backplane card with a shelf controller card for providing cross-connects between processor cards. Multiple shelves may be interconnected to form a large computer system.

Abstract: This invention provides a method and apparatus for issuing or renewing a host address. The apparatus has an input device to receive a data packet having a host identifier, a memory to store a list of host identifiers, and a processor to match the host identifier with the list of host identifiers. If a match is found, an output device transmits the data packet to an address allocation device to issue or renew the host address. The method provides for retrieving the host identifier in the header of the data packet, matching the host identifier with a list of host identifiers, and maintaining a state of authentication for the host if a match is found, otherwise maintaining a state of unauthentication for the host. The method further provides for inserting a proxy address in a relay agent address field, setting a flag, and transmitting the data packet to an address allocation device to issue or renew the host address.

Abstract: One embodiment provides a system which uses a temporal ordering policy for allocation of limited processor resources. The system starts by executing instructions for a program during a normal-execution mode. Upon encountering a condition which causes the processor to enter a speculative-execution mode, the processor performs a checkpoint and commences execution of instructions in the speculative-execution mode. Upon encountering an instruction which requires the allocation of an instance of a limited processor resource during the execution of instructions in the speculative-execution mode, the processor checks a speculative-use indicator associated with each instance of the limited processor resource. Upon finding the speculative-use indicators asserted for all instances of the limited processor resource which are available to be allocated for the instruction, the processor aborts the instruction.

Abstract: A method for handling input/output (I/O) commands in a storage system includes establishing first and second counters for counting unfinished I/O commands, and establishing a reference which is initially set to the first counter. The reference is periodically switched between the first counter and the second counter, and the switching interval is less than the I/O timeout value. Upon placing an I/O command into an I/O command queue, a copy of the current reference is made into an I/O specific control block and the current referenced counter is incremented. Upon finishing of an I/O command, the counter referenced by the I/O specific control block is decremented and the I/O command is removed from the I/O command queue. When switching the reference, a problem is detected in the event that the counter being switched to is above a predetermined threshold. Upon detection of a problem, a more explicit I/O check is conducted.

Abstract: A method for switching KVM switch ports comprising a plurality of computer ports and a related device are provided. A behavior of a mouse coupled to the KVM switch is detected. The behavior comprises multiple click on a specific button of the mouse. In response to the behavior, the computer ports are switched accordingly.

Abstract: Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller.

Abstract: A method and apparatus for low latency transport of signals. In some embodiments a method may include providing a buffer controller between two consecutive signal transmission processes between a host and a client to synchronize a write from a first of the two consecutive signal transmission processes and a read to a second of the of the two consecutive signal transmission processes, wherein the buffer controller includes a first buffer, a second buffer, and a first status list and a second status list that each provide an association status of the first buffer and the second buffer.

Abstract: Systems and methods of controlling control and/or monitoring devices are provided. A controller can include a software defined radio in order to communicate with control and/or monitoring devices that employ different communication protocols. The controller can be in the form of a memory stick, memory card or dongle.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: Embodiments of the present invention may provide for architectural and compiler approaches to optimizing processors by packing instructions into instruction register files. The approaches may include providing at least one instruction register file, identifying a plurality of frequently-used instructions, and storing at least a portion of the identified frequently-used instructions in the instruction register file. The approaches may further include specifying a first identifier for identifying each of instructions stored within the instruction register file, and retrieving at least one packed instruction from an instruction cache, wherein each packed instruction includes at least one first identifier. The packed instructions may be tightly packed or loosely packed in accordance with embodiments of the present invention. Packed instructions may also be executed alongside traditional non-packed instructions.

Abstract: Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

Abstract: A system comprising a communication (COM) port server that, together with a COM port client, establishes COM port redirection over a network and communicates data with a serial port, at least one embedded application which is configured to communicate data via a serial port, and at least one virtual serial port application communicatively coupled to the embedded application and the COM port server. The virtual serial port application translates data communicated between the COM port server and the embedded application as if the COM port server and the embedded application were connected by a serial communication link.

Abstract: An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.

Abstract: A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Abstract: Provided is a method for using host and storage controller port information to configure paths between a host and storage controller. Information is gathered on ports on at least one host, ports on at least one storage controller managing access to storage volumes, and at least one fabric over which the at least one host and storage controller ports connect. For at least one host port and storage controller port, information is gathered on a connection metric related to a number of paths in which the port is configured and a traffic metric indicating Input/Output (I/O) traffic at the port. A determination is made of available ports for one host and storage controller that are available to provide paths between one host and storage controller. The connection and traffic metrics for the available host ports are processed to select at least one host port. The connection and traffic metrics for the available storage controller ports are processed to select at least one storage controller port.

Abstract: A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.

Abstract: A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

Abstract: The invention proposes a storage apparatus and conversion board that can increase the number of hard disk drive heads in a given, limited space for installation of disk units in the storage apparatus, and can consequently improve data read/write performance. A storage apparatus has a plurality of first disk units of a specific size, each removable, and a controller that controls data read/write from/to the first disk units, and the storage apparatus includes: external connectors, each provided in corresponding positions where the first disk units are installed, and physically and electrically connected with the first disk units installed in a specific state; and a removable conversion unit provided in one or more of the external connectors, and used for installing, in the position where one or more of the first disk units are to be installed, a larger number of second disk units, each smaller in physical size, than the one or more first disk units.

Abstract: One embodiment of the present invention sets forth a technique for reducing the latency associated with media protection notification for serial interface mass storage devices, such as serial AT attachment (SATA) hard disk drives. A new link layer primitive, referred to as hold-emergency (HOLDE), incorporates the flow-control behavior of the existing HOLD command, with the additional new action of notifying the hard disk drive to take emergency steps to prepare for impact. The HOLDE link layer primitive operates in conjunction with the existing hold-acknowledge (HOLDA) primitive and is semantically similar to the existing HOLD primitive. The HOLDE mechanism is preferably implemented directly in hardware in the SATA link layer state machines within the host and the hard disk drive.