Abstract: A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.

Abstract: An organic photodetector includes: a first electrode; a second electrode facing the first electrode; an activation layer between the first electrode and the second electrode; a hole injection layer between the first electrode and the activation layer; and a hole transport layer between the hole injection layer and the activation layer, wherein the hole transport layer includes: a first hole transport layer including a p-dopant; and a second hole transport layer not including a p-dopant.

Abstract: A method of manufacturing a power semiconductor device includes forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate hole, a source hole, and a drain hole penetrating the passivation layer in a same process step; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern may be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern may have a step difference.

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: There is provided a semiconductor device which includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.

Abstract: A display device, comprising: a flexible display module (4), a fixing frame (11) and a bending frame (12). The flexible display module comprises a first planar region (41), a second planar region (43), and a first bending region (42) between the first planar region and the second planar region. The fixing frame comprises a first frame (111) for fixing the first planar region and a second frame (112) for fixing the second planar region. The bending frame comprises a first deformation frame (31), a first bending frame (121), a second deformation frame (32), a second bending frame (122), and a bending mechanism (123) between the first bending frame and the second bending frame, the first bending frame being fixed to the first frame by means of first deformation frame, second bending frame being fixed to the second frame by means of second deformation frame.

Abstract: A magnetic domain wall movement element includes: a laminate including a ferromagnetic layer, a non-magnetic layer, and a magnetic domain wall movement layer; a first conductive layer; and a first surface layer laminated above a substrate in order from the substrate, wherein the non-magnetic layer is sandwiched between the ferromagnetic layer and the magnetic domain wall movement layer, wherein the first conductive layer is connected to an upper surface of the magnetic domain wall movement layer, wherein the first surface layer contacts at least a part of an upper surface of the magnetic domain wall movement layer, and wherein the resistivity of the first surface layer is higher than the resistivity of the magnetic domain wall movement layer.

Abstract: According to one embodiment, a memory device includes a memory cell including a magnetoresistive effect element. The magnetoresistive effect element includes a non-magnetic layer between first and second electrodes in the first direction, a first magnetic layer between the first electrode and the non-magnetic layer, a second magnetic layer between the second electrode and the non-magnetic layer, and a first layer between the second electrode and the second magnetic layer. The first layer includes oxygen and at least one selected from magnesium, transition metal, and lanthanoid, the first layer has a first size in the first direction, the non-magnetic layer has a second size in the first direction. The first size is 1.1 times or more and 2 times or less the second size.

Abstract: A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

Abstract: A through electrode substrate includes a substrate having a through hole extending through between a first face and a second face, a diameter of the through hole not having a minimum value inside the through hole; and a conductor arranged inside the through hole, wherein the through hole has a shape having a value obtained by summing a first to an eighth inclination angle at a first to an eighth position, respectively, of an inner face of the through hole of 8.0° or more, each of the first to the eighth inclination angle is an angle of the inner face with respect to a center axis of the through hole, and the first to the eighth position correspond to positions at distances of 6.25%, 18.75%, 31.25%, 43.75%, 56.25%, 68.75%, 81.25%, and 93.75%, respectively, from the first face in a section from the first face to the second face.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprises an upper portion directly above and joined with a lower portion. The individual TAVs in a vertical cross-section comprises at least one external upper jog surface. The individual TAVs comprise at least one external lower jog surface in the conductor tier in the vertical cross-section and that is below the upper jog surface. Other embodiments, including method, are disclosed.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.

Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets (NS) and a method of forming such a structure. The structure is a three dimensional (3D) integration by vertically stacking nFETs and pFETs for area scaling. In an embodiment, vertically-stacked NS FET structures include a first nanosheet transistor located above a second nanosheet transistor; the first nanosheet transistor including a first NS channel material, wherein the first NS channel material includes a first crystalline orientation; the second nanosheet transistor including a second NS channel material, wherein the second NS channel material comprises a second crystalline orientation, the first crystalline orientation is different from the second crystalline orientation. In an embodiment, each of the respective formed vertically-stacked NS FET structures include respective suspended stack of nanosheet channels that are self-aligned with each other.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: The present application discloses a driving substrate, a manufacturing method thereof, and a display panel. The driving substrate comprises a substrate, a first thin film transistor, a second thin film transistor, a first capacitor, and a second capacitor. The first thin film transistor comprises a first gate electrode first capacitor located on the substrate, the first capacitor comprises a first electrode plate and a second electrode plate, the second electrode plate is located above the first electrode plate, the first gate electrode is also used as the first electrode plate, the second capacitor comprises a second electrode plate and a third electrode plate, and the third electrode plate is located above the second electrode plate.