Patents Examined by Niki H Nguyen
  • Patent number: 11990335
    Abstract: A process for fabricating a single-crystal semiconductor material of group 13 nitride, in particular GaN, including the steps of: deposition of at least one single-crystal layer by three-dimensional epitaxial growth on a starting substrate, the layer including areas resulting from the growth of basal facets, and areas resulting from the growth of facets of different orientations, called non-basal facets; supply of an n-dopant gas including a first chemical element selected from the chemical elements of group 16 of the periodic table, and at least one second chemical element selected from the chemical elements of group 14 of the periodic table, such that the concentration of the second element in the areas resulting from the growth of the basal facets is higher than 1.0×1017/cm3, and the concentration of the first element in the areas resulting from the growth of the non-basal facets is lower than 2.0×1018/cm3.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 21, 2024
    Assignee: IVWORKS CO., LTD.
    Inventors: Bernard Beaumont, Jean-Pierre Faurie, Vincent Gelly, Nabil Nahas, Florian Tendille
  • Patent number: 11978688
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.
    Type: Grant
    Filed: October 16, 2022
    Date of Patent: May 7, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jumyong Park, Solji Song, Jinho An, Jeonggi Jin, Jinho Chun, Juil Choi
  • Patent number: 11967948
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 23, 2024
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Michael A Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Robert B. Welstand, Mark L. Burgener
  • Patent number: 11968868
    Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of pixel island regions spaced apart from each other. A plurality of connection bridge regions connecting adjacent ones of the pixel island regions to each other. At least one of the connection bridge regions includes a first metal layer, a second metal layer, and a third metal layer disposed in a stacked arrangement, and each of the first metal layer, the second metal layer, and the third metal layer is patterned into at least one metal trace.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: April 23, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Likun Cheng, Liang Sun, Shijuan Yi
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Patent number: 11961776
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a connector structure configured for carrying a signal and providing a semiconductor die. At least a portion of the connector structure and the semiconductor die are encapsulated with an encapsulant. The semiconductor die is interconnected with the connector structure by way of a conductive trace.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 16, 2024
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Scott M. Hayes
  • Patent number: 11961825
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Aparna U. Limaye, Dong Soon Lim, Randon K. Richards, Owen R. Fay
  • Patent number: 11955444
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. The semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. The semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. The semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Manikandan Arumugam, Tsung-Yi Yang, Chien-Chih Chen, Mu-Han Cheng, Kuo-Hsien Cheng
  • Patent number: 11955526
    Abstract: An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Kangguo Cheng, Julien Frougier, Chanro Park, Veeraraghavan S. Basker
  • Patent number: 11952372
    Abstract: Provided is a tribenzazole amine derivative represented by Formula 1 that effectively absorbs high energy UV light from an external light source to minimize damage to organic materials present in an organic electroluminescent device, contributing to a substantial improvement in the lifetime of the organic electroluminescent device. Also provided is an organic electroluminescent device using the tribenzazole amine derivative. The organic electroluminescent device includes a first electrode, a second electrode, and an organic layer arranged between the first and second electrodes. The organic layer includes the tribenzazole amine derivative.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 9, 2024
    Assignee: LAPTO CO., LTD.
    Inventors: Moon-ki Seok, Byung-soo Go, Chul-soo Lim, Hyun-a Kim, Kyou-sic Kim, Yong-pil Park, Kap-jong Han, Eu-gene Oh
  • Patent number: 11948921
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: April 2, 2024
    Inventors: Randon K. Richards, Aparna U. Limaye, Owen R. Fay, Dong Soon Lim
  • Patent number: 11950500
    Abstract: The present disclosure relates to an organic light emitting diode that includes at least one emitting material layer including an anthracene-based host and a boron-based dopant, at least one electron blocking layer including an amine-based compound substituted with at least one polycyclic aryl group, and optionally at least one hole blocking layer including an azine-based compound or a benzimidazole-based compound. The organic light emitting diode has enhanced luminous efficiency as well as excellent luminous lifetime.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: April 2, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Seung Hee Yoon, In Bum Song, Jin Ho Park, Dong Hyeok Lim
  • Patent number: 11950431
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Patent number: 11943973
    Abstract: Disclosed are a preparation method of a display panel, a display panel and a displaying device. The display panel comprises a plurality of first-color subpixels, and each first-color subpixel comprises a base, the base comprising a first driving electrode and a second driving electrode; a flat layer disposed on the side, near the first driving electrode and the second driving electrode, of the base; a patterned passivation layer and at least one first electrode disposed on the side, away from the base, of the flat layer, the first electrode being connected with the first driving electrode through via holes penetrating the flat layer; and at least one second electrode disposed on the side, away from the base, of the passivation layer, the second electrode being connected with the second driving electrode through via holes penetrating the passivation layer and the flat layer.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 26, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yongfeng Zhang, Xue Dong, Zhiqiang Jiao, Lei Zhao, Jiushi Wang
  • Patent number: 11943958
    Abstract: A display panel according to one embodiment of the disclosure includes: a flexible substrate; a plurality of self-luminescent elements; a plurality of TFT circuits provided between the flexible substrate and the plurality of self-luminescent elements; a first inorganic film covering each of the TFT circuits; a second inorganic film covering each of the self-luminescent elements; and a resin layer covering the second inorganic film and covering at least a portion of the first inorganic film in contact with an end portion of the second inorganic film. The first inorganic film is provided between the plurality of TFT circuits and the plurality of self-luminescent elements, and has a step portion. The step portion is a thinned portion of the first inorganic film opposed to an end portion of the flexible substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: March 26, 2024
    Assignee: JOLED INC.
    Inventors: Yuichiro Ishiyama, Takahiro Seki
  • Patent number: 11916037
    Abstract: A method for bonding semiconductor devices is provided. The method may include several operations. A wafer and a chip are formed. The wafer and the chip are disposed in a low-pressure environment. A planar surface of the chip is moved toward a planar surface of the wafer. A void is formed between the planar surface of the chip and the planar surface of the wafer. The chip is bonded to the wafer. A bonded structure of the chip and the wafer is disposed under a standard atmosphere and a size of the void is reduced. A system for forming a semiconductor structure is also provided.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jen-Yuan Chang
  • Patent number: 11915987
    Abstract: A semiconductor device including a power supply circuit to supply power to a circuit formed on a main substrate equipped with a circuit module is made smaller in size. A semiconductor device includes: a circuit module including a module substrate and a circuit element mounted on the module substrate; and a main substrate on which the circuit module is mounted. The semiconductor device further includes a power supply circuit to supply power to at least a circuit formed on the module substrate. The power supply circuit includes: a voltage generating circuit to output a predetermined output voltage; a first capacitor; and a second capacitor larger in capacity than the first capacitor. The voltage generating circuit and the first capacitor are mounted on the module substrate. The second capacitor is mounted on the main substrate.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 27, 2024
    Assignee: AISIN CORPORATION
    Inventor: Takanobu Naruse
  • Patent number: 11910704
    Abstract: An organic light emitting diode device and a display panel are provided. The display panel includes the organic light emitting diode device. The organic light emitting diode device includes an emitting material layer. The emitting material layer includes a first common blue-light light-emitting layer, a red-green-blue light emitting layer, and a second common blue-light light-emitting layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 20, 2024
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Shengfang Liu, Weiwei Li, Mugyeom Kim
  • Patent number: 11908715
    Abstract: A temperature-controlled substrate support for a substrate processing system includes a substrate support located in the processing chamber. The substrate support includes N zones and N resistive heaters, respectively, where N is an integer greater than one. A temperature sensor is located in one of the N zones. A controller is configured to calculate N resistances of the N resistive heaters during operation and to adjust power to N?1 of the N resistive heaters during operation of the substrate processing system in response to the temperature measured in the one of the N zones by the temperature sensor, the N resistances of the N resistive heaters, and N?1 resistance ratios.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 20, 2024
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Sairam Sundaram, Aaron Durbin, Ramesh Chandrasekharan
  • Patent number: 11905300
    Abstract: The present disclosure relates to a compound, a material for an organic electroluminescent device and an application thereof. The compound provided by the present disclosure has a relatively high refractive index and can effectively improve the light extraction efficiency and the external quantum efficiency of an organic electroluminescent device when used in the organic electroluminescent device especially as a material for the capping layer. The compound has a relatively high refractive index in the region of visible light (400-750 nm), which is conducive to improving the light-emitting efficiency. The compound has a relatively large extinction coefficient in the ultraviolet region (less than 400 nm), which is conducive to absorbing harmful light and protecting eyesight and has a relatively small extinction coefficient in the region of blue light (400-450 nm) and hardly absorbs blue light, which is conducive to improve the light-emitting efficiency.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: February 20, 2024
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Lu Zhai, Wei Gao, Wenpeng Dai, Lei Zhang, Quan Ran