Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.

Abstract: A semiconductor photomultiplier module (20; 30; 40) comprises a first semiconductor chip (21; 31; 41) disposed in a first plane and comprising an array (21.1) of single-photon avalanche diodes (SPAD), a second semiconductor chip (22; 32; 42) disposed in a second plane and comprising a first part of an electronic read-out circuit, and a third semiconductor chip (26; 36; 46) comprising a second part of the electronic read-out circuit, wherein the first semiconductor chip (21; 31; 41) and the second semiconductor chip (22; 32; 42) are arranged in a stacked relationship and vertical electrical interconnects (23) are arranged to electrically interconnect the first semiconductor chip (21; 31; 41) with the second semiconductor chip (22; 32; 42).

Abstract: The circular polarizer may be omitted from a display to increase efficiency. A polarizer-free display may use other non-polarizer techniques to mitigate reflections of ambient light and mitigate diffraction reflection artifacts. The polarizer-free display may include a black pixel definition layer that absorbs ambient light. Color filter elements may be included in a black matrix to mitigate ambient light reflections. An intra-anode phase shift layer and/or an inter-anode phase shift layer may be included in the display to mitigate diffractive reflection artifacts. Multiple sub-pixels of the same color may be used in a single pixel to ensure a neutral reflection color. The display may include a cathode layer that is patterned to have openings over the black pixel definition layer to mitigate reflections. The display may include diffusive particles (in the color filter element or in a separate diffuser layer) to mitigate diffractive reflection artifacts.

Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Abstract: An integrated semiconductor packaging system includes: a first wet clean tool configured to perform a first wet clean process on a frame, wherein a plurality of top dies are disposed on the frame; a second wet clean tool configured to perform a second wet clean process on a wafer, wherein a plurality of bottom dies corresponding to the plurality of top dies, respectively, are disposed on the wafer; a pick-and-place tool configured to bond the plurality of top dies to the plurality of bottom dies, respectively; and a first transmission path through which the frame and the wafer are transferred from the first wet clean tool and the second wet clean tool to the pick-and-place tool, respectively, wherein the frame is directly transferred from the first wet clean tool to the pick-and-place tool, and the wafer is directly transferred from the second wet clean tool to the pick-and-place tool.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a first semiconductor substrate. The method also includes forming a first conductive pad over the first semiconductor substrate. The method further includes forming a first hybrid bonding pad on the first conductive pad, wherein the first hybrid bonding pad includes nano-twins copper, and a thickness of the first hybrid bonding pad is less than a thickness of the first conductive pad.

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A first substrate is provided. A first dielectric structure is formed on the first substrate. At least one first cavity is formed in the first dielectric structure. A first stress adjustment layer is formed in the first cavity. The first stress adjustment layer covers the first dielectric structure. A second substrate is provided. A second dielectric structure is formed on the second substrate. At least one second cavity is formed in the second dielectric structure. A second stress adjustment layer is formed in the second cavity. The second stress adjustment layer covers the second dielectric structure. The first stress adjustment layer and the second stress adjustment layer are bonded.

Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

Abstract: There are provided a semiconductor and a method of fabricating the same. The semiconductor device may include a second semiconductor substrate directly bonded to a first semiconductor substrate. The first semiconductor substrate may include a first through via with an end portion protruding through a first top surface, the first top surface being a top surface of a first semiconductor substrate body, a liner extending to partially expose a side surface of the end portion of the first through via, and a first diffusion barrier layer. The liner may include a third top surface that is positioned at a lower height than a second top surface, the second top surface being a top surface of the end portion of the first through via and substantially equal to the first top surface. Alternatively, the liner may include a third surface positioned at a height that is lower than the second top surface and higher than the first top surface.

Abstract: A drive circuit substrate, LED display panel and method of forming the same and display device are provided, in field of display technologies. The drive circuit substrate includes a base substrate and drive electrodes arranged in an array on a surface of the base substrate, where at least one conductive structure is arranged on a surface of each drive electrode away from the base substrate, the conductive structure is electrically connected to corresponding drive electrode. The driving electrodes include first and second driving electrodes, horizontal height of first driving electrode is greater than horizontal height of second driving electrode. The conductive structure includes first conductive structure on a surface of the first driving electrode away from the base substrate and second conductive structure on a surface of the second driving electrode away from the base substrate, height of second conductive structure is greater than height of first conductive structure.

Abstract: A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.

Abstract: A method of manufacturing a power semiconductor device includes forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate hole, a source hole, and a drain hole penetrating the passivation layer in a same process step; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern may be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern may have a step difference.

Abstract: An organic photodetector includes: a first electrode; a second electrode facing the first electrode; an activation layer between the first electrode and the second electrode; a hole injection layer between the first electrode and the activation layer; and a hole transport layer between the hole injection layer and the activation layer, wherein the hole transport layer includes: a first hole transport layer including a p-dopant; and a second hole transport layer not including a p-dopant.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: A magnetic domain wall movement element includes: a laminate including a ferromagnetic layer, a non-magnetic layer, and a magnetic domain wall movement layer; a first conductive layer; and a first surface layer laminated above a substrate in order from the substrate, wherein the non-magnetic layer is sandwiched between the ferromagnetic layer and the magnetic domain wall movement layer, wherein the first conductive layer is connected to an upper surface of the magnetic domain wall movement layer, wherein the first surface layer contacts at least a part of an upper surface of the magnetic domain wall movement layer, and wherein the resistivity of the first surface layer is higher than the resistivity of the magnetic domain wall movement layer.

Abstract: A display device, comprising: a flexible display module (4), a fixing frame (11) and a bending frame (12). The flexible display module comprises a first planar region (41), a second planar region (43), and a first bending region (42) between the first planar region and the second planar region. The fixing frame comprises a first frame (111) for fixing the first planar region and a second frame (112) for fixing the second planar region. The bending frame comprises a first deformation frame (31), a first bending frame (121), a second deformation frame (32), a second bending frame (122), and a bending mechanism (123) between the first bending frame and the second bending frame, the first bending frame being fixed to the first frame by means of first deformation frame, second bending frame being fixed to the second frame by means of second deformation frame.

Abstract: There is provided a semiconductor device which includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.