Patents Examined by Niki T Nguyen
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Patent number: 12295204Abstract: The circular polarizer may be omitted from a display to increase efficiency. A polarizer-free display may use other non-polarizer techniques to mitigate reflections of ambient light and mitigate diffraction reflection artifacts. The polarizer-free display may include a black pixel definition layer that absorbs ambient light. Color filter elements may be included in a black matrix to mitigate ambient light reflections. An intra-anode phase shift layer and/or an inter-anode phase shift layer may be included in the display to mitigate diffractive reflection artifacts. Multiple sub-pixels of the same color may be used in a single pixel to ensure a neutral reflection color. The display may include a cathode layer that is patterned to have openings over the black pixel definition layer to mitigate reflections. The display may include diffusive particles (in the color filter element or in a separate diffuser layer) to mitigate diffractive reflection artifacts.Type: GrantFiled: May 25, 2022Date of Patent: May 6, 2025Assignee: Apple Inc.Inventors: Young Cheol Yang, Bhadrinarayana Lalgudi Visweswaran, Michelle C Sherrott, Fuyi Yang
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Patent number: 12150322Abstract: An imaging device according to an embodiment of the present disclosure includes: a first semiconductor substrate (100) provided with pixels including a photoelectric conversion element (PD) and floating diffusion (FD) that temporarily holds a charge output from the photoelectric conversion element (PD); and a semiconductor layer (200Y) provided on the first semiconductor substrate (100) via an insulating film (123), the semiconductor layer (200Y) including a readout circuit unit (539) that reads out the charge held in the floating diffusion (FD) and outputs a pixel signal, in which the semiconductor layer (200Y) is formed of an organic semiconductor material.Type: GrantFiled: June 17, 2020Date of Patent: November 19, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kenya Nishio, Suguru Saito, Nobutoshi Fujii, Hirotaka Yoshioka
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Patent number: 12107120Abstract: A power semiconductor device includes a substrate, including an active region and edge regions, including a semiconductor layer of a first conductive type including silicon carbide (SiC); an insulating film disposed on the edge regions; a field plate pattern disposed on the insulating film; a first doped region of a second conductive type disposed inside the substrate to extend downward from a top surface of the edge regions; a second doped region of the second conductive type, buried in the edge regions, extends in a direction having a vector component parallel to the top surface of the substrate; and a third doped region of the first conductive type is disposed on the second doped region and at a side portion of the first doped region.Type: GrantFiled: December 13, 2021Date of Patent: October 1, 2024Assignee: Hyundai Mobis Co., Ltd.Inventors: Tae Youp Kim, Hyuk Woo
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Patent number: 11482485Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.Type: GrantFiled: October 18, 2020Date of Patent: October 25, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin
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Patent number: 11040872Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.Type: GrantFiled: October 8, 2019Date of Patent: June 22, 2021Assignee: Infineon Technologies AGInventors: Claus Waechter, Edward Fuergut, Bernd Goller, Michael Ledutke, Dominic Maier
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Patent number: 10943948Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.Type: GrantFiled: January 30, 2019Date of Patent: March 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
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Patent number: 10872906Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.Type: GrantFiled: March 13, 2019Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Hung, Pei-Wei Lee, Pang-Yen Tsai