Abstract: An Operating System (OS) function maps affinity to processors for each new task and except for certain circumstances where other processors are permitted to steal tasks, this affinity remains unchanged. Hierarchical load balancing is mapped through an affinity matrix (that can be expressed as a table) which is accessed by executable code available through a dispatcher to the multiplicity of instruction processors (IPs) in a multiprocessor computer system. Since the computer system has multiple layers of cache memories, connected by busses, and crossbars to the main memory, the hierarchy mapping matches the cache memories to assign tasks first to IPs most likely to share the same cache memory residue from related tasks, or at least less likely to incur a large access time cost. Each IP has its own switching queue (SQ) for primary task assignments through which the OS makes the initial affinity assignment.

Abstract: The invention relates to a process for assigning tasks in a multiprocessor digital data processing system having a preemptive operating system, and an architecture for implementing the process. The system comprises processors (200–203, 210–213) capable of processing the tasks in parallel, divided into groups (200–201, 202–203). An elementary queue (5a, 5b) is associated with each of the processor groups (200–201, 202–203) and stores tasks to be executed. All the tasks to be executed (T1 through T10) are stored in a table (4). Each of the tasks (T1 through T10) of the table (4) is associated with one of the queues (5a, 5b) and each of the tasks stored in the queues (5a, 5b) is associated with one of the processors (200 through 201). The associations are made by sets of cross pointers (p200 through p203, pp5a, pp5b, pT1, pT5, pT10, p5a1 through p5a4, and p5b1 through p5b10).

Abstract: Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received.

Abstract: Methods and apparatus for implementing a virtual machine that supports the execution of more than one application per virtual machine process are described. According to one aspect of the present invention, a computing system includes a processor, a memory, and a virtual machine that is in communication with the processor. The virtual machine is arranged to enable one or more jobs to run on the virtual machine, and is further arranged to create a heap in the memory for each job that runs on the virtual machine. In one embodiment, the virtual machine includes a jobs manager, a class manager, and a heap manager. In such an embodiment, the heap manager manages substantially all heaps in the memory that are created by the virtual machine.

Abstract: A method and system allocate resources in a plurality of processors system. When a processor is idle, the system determines when another processor is not idle. The time the non-idle processor remains non-idle is timed, and once a predetermined amount of time elapses, if the non-idle processor is still not idle, the idle processor poaches a job from the non-idle processor.

Abstract: A real time control system capable of accurately supporting the real time characteristics of a multitasking digital signal processor (DSP) which requires an operating system (OS), is provided. In this real time control system, a ready queue and a waiting queue each includes a priority link having information indicating the first task control block and the last task control block among task control blocks of the same priority in a multitasking environment, and a queue link having information indicating the first task control block and the last task control block among tasks for a DSP according to the purpose of use. Timer control blocks are managed using a timer wheel having a pointer arrangement structure. A memory is divided into an internal memory and an external memory, and thus the internal and external memories are managed respectively at user request.

Abstract: An object-based multi-threaded computing system has a cyclic garbage collection strategy and includes an object locking system having (i) a first mode in which access by a single thread without contention to an object is controlled by a monitor internal to said object, and (ii) a second mode in which access by multiple threads with contention to said object is controlled by a monitor external to said object. For any given object a transition from the first mode to the second mode is termed inflation, and a transition from the second mode to the first mode is termed deflation. Responsive to the start of a period of contention for an object in said first mode, the object is inflated to the second mode, and an inflation rate counter is incremented. After the period of contention has concluded the value of the inflation rate counter is compared against a predetermined value in order to determine whether or not to deflate the object. The inflation rate counter is reset at every garbage collection cycle.

Abstract: A system for embedding auxiliary digital information (Di) into an existing primary digitally encoded signal (Xn) to form an unobjectionable composite digital signal (Cn). Auxiliary data bits (Di) modulate a pseudo-random (e.g., PN) sequence (125) to provide an auxiliary data sequence (160) that is used to modify the Least Perceptually Significant Bits (LPSBs) (180) of successive multi-bit samples (120) of the primary signal. In a cross-term compensation embodiment (300, 400, 1000), a correlation (V) between the PN sequence and the sample bits is determined, and compared to the auxiliary data bits (Di) to determine whether there is a desired correspondence. The LPSBs in the samples are toggled (360), if necessary, to provide the desired correspondence. The selection of LPSBs to modify accounts for a desired noise level of the auxiliary data (Di) in the primary signal (Xn).