Abstract: The present invention relates to a device for reducing power consumption of a monitor and the method thereof. The device for reducing power consumption of a monitor according to the present invention comprises a control unit which generates a power-saving mode signal according to the control signal inputted from an external signal source; a first switching unit, connected to said control unit, which turns on or off the power according to said power-saving mode signal, in which said power is supplied from the power-supply terminal to the deflection drive terminal; a second switching unit which turns on or off the power supplied from the power-supply terminal to the heater, in which said switching unit operates in the same manner as the first switching unit; and a voltage-drop unit, connected between said power-supply terminal and said heater, which lowers the voltage applied from said power-supply terminal only when said second switching unit is off, and then supplies the same to said heater.

Abstract: A battery pack includes overcurrent limiting transistors and respective sensors in proximity to battery cell and the transistors. A CPU in the battery pack receives temperature signals from the sensors and selects an action to control temperature based on the temperature signals.

Abstract: A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.

Abstract: A computer system is disclosed having a bus capability determination mechanism. In a preferred embodiment, the computer system includes a backplane having sockets into which system and peripheral boards may be inserted. The sockets are coupled together by a backplane bus that includes a bus capability line. Each board preferably includes a voting circuit that, when enabled, limits the voltage on the capability signal line to no more than a predetermined voltage that is indicative of the capability of the board. The voltage on the capability signal line will thus be determined by the board having the lowest voltage limit. The clock source for the bus can then be set to the clock rate indicated by the voltage on the capability signal line. Zener devices are preferably used to carry out the voting operation, and may be disabled after the voting operation is complete.

Abstract: Systems, devices and methods are provided for expanding an interface to a computer. According to one aspect, a device is provided, including a backplane and at least one expansion card. The backplane includes at least one expansion slot and an upstream connector for connecting with the computer. The expansion card is adapted for coupling with the expansion slot. The expansion card includes at least one port to provide an interface with the computer. According to one aspect, an apparatus is provided, including a control module, a hub coupled to the control module and adapted for providing USB/USB+ outputs, and an external functions unit coupled to the hub and adapted for providing outputs.

Abstract: System (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a high-speed clock to the high-speed functional block (51). The system (50) further comprises a peripheral bus (59), a low-speed functional block (52) operably linked to this peripheral bus (59), a circuitry (53) for generating a wait signal (PWAIT), a low-speed clock line (57) for applying a low-speed clock (PCLK) to the low-speed functional block (52), a select line (58) for feeding a select signal (PSEL) from the peripheral bus (59) to the low-speed functional block (52), an enable line (55) for applying a clock enable signal (PCLKEN) to the circuitry (53), and a wait line (61) for feeding the wait signal (PWAIT) to the high-speed functional block (51). The circuitry (53) generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).