Abstract: A method is presented that enhances the survivability of system software components, even in the event of catastrophic failure of the computing element on which they reside. In particular, the combination of a distributed operating system (Non Stop Clusters) and a fault-tolerant interconnect (ServerNet) provides an environment conducive to posthumous recovery strategies that have been unavailable in previous distributed computing environments. The specific strategy outlined here is called resource harvesting, and involves a novel approach that retrieve critical data structures of memory from a failed computing element for reconstruction on a non-failed computing element, allowing such critical data structures to continue with their original function.

Abstract: Security vulnerabilities of one or more target hosts are assessed by a remote or local host via a server. The hosts and the server are coupled to the internet and communicate via hypertext pages and email. A user at an arbitrary host on the internet inputs data identifying the user and/or the arbitrary host, and the target host. A network address is obtained for the user and a certification file such as Internic can be checked to determine a network address of the user and confirm that the user is authorized to assess the security vulnerabilities of the target host. A facts file is built on the server by polling the services available at the target host, including inquiries to the various ports of the TCP subsystem, for building a table of services and responses. A security algorithm compares the responses to stored data for identifying likely security vulnerabilities.

Abstract: A virtual private network for communicating between a server and clients over an open network uses an applications level encryption and mutual authentication program and at least one shim positioned above either the socket, transport driver interface, or network interface layers of a client computer to intercept function calls, requests for service, or data packets in order to communicate with the server and authenticate the parties to a communication and enable the parties to the communication to establish a common session key. Where the parties to the communication are peer-to-peer applications, the intercepted function calls, requests for service, or data packets include the destination address of the peer application, which is supplied to the server so that the server can authenticate the peer and enable the peer to decrypt further direct peer-to-peer communications.

Abstract: Complex resource configurations often exist in multiprocessor systems. As a result thereof, coordination problems arise given competing accesses to a specific resource configuration by a plurality of processors. In a method for the coordination of parallel accesses of a plurality of processors to resource configurations a central security table is introduced. A processor must deposit its processor number thereat for a specific security number if the processor is to receive control over the resource configuration belonging to this security number.

Abstract: A fault-tolerant transaction processing system and method stores records associated with operations of the system in order to permit recovery in the event of a need to roll back a transaction or to restart the system. At least some of the operational records are stored as a recovery log in low-speed non-volatile storage and at least some are stored as a recovery list in high speed volatile storage. Rollback of an individual transaction is effected by reference to the recovery list whereas restart of the system is effected by reference to the recovery log.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to by organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into single monolithic entity.

Abstract: An electronic system that remains disabled after power-on until its user is recognized. The electronic system includes a host processor and a deactivation circuit coupled to the host processor. The deactivation circuit places the host processor into an inoperative state until the user is recognized. In one embodiment, the deactivation circuit is a security processor coupled to a reset input of the host processor. The security processor includes a processing unit and an internal memory unit to contain software required by the host processor to complete a booting procedure.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: The present inventions provides a method and apparatus for analyzing serial data. The invention comprises a serial analyzer which receives serial data from a logic analyzer. The serial analyzer processes the data to convert the serial data into parallel words. A listing tool receives the parallel words and generates a listing to be displayed. The listing generated is arranged in a first column and the sampled serial data is in a second column, so that, a user may view simultaneously the parallel word and the serial data corresponding to it. The listing tool also receives a time and state at which each bit of serial data was captured by the logic analyzer. The listing tool arranges the time of each bit of serial data in a third column, and the state at which each bit of serial data occurred in a fourth column. Thus, the user may simultaneously view on a display the parallel words, the sampled serial data, the time of capture, and the states corresponding to each bit in the serial data.

Abstract: A fault tolerant recoverable connection device and methods are disclosed that include a primary router in an active state to provide a connection between clients and servers in a network, and a backup router in a standby state. The states of the primary and backup routers are switched when the primary router fails, the backup router has a better reach-ability state than the primary router, or by an operator command. Each router has a synchronization manager which maintains synchronized tables between the active and standby routers; a monitoring manager which monitors and switch the state of the routers; a reach-ability manager which monitors, updates, and compares the reach-ability set and state of the routers; and a keep alive manager which monitors the routers to provide a status notification to the monitoring manager.

Abstract: Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising at least two memory half-matrices, a bidirectional internal bus for the transmission of data to and from the memory half-matrices, a programming unit for each one of the at least two memory half-matrices, and a data sensing unit. The programming units are adapted to program the at least two memory half-matrices and the data sensing unit and the programming units communicate with the bidirectional internal bus to reroute onto the bus reading data and programming data of the at least two memory half-matrices.

Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and-columns-to be prepared are substituted with redundant memory columns.

Abstract: A system for recovery of process relationships following node failure within a computer cluster is provided. For relationship recovery, each node maintains set of care relationships. Each relationship is of the form carer cares about care target. Care relationships describe process relations such as parent-child or group leader-group member. Care relationships are stored at the origin node of their care targets. Following node failure, a surrogate origin node is selected. The surviving nodes then cooperate to rebuild vproc structures and care relationships for the processes that originated at the failed node at the surrogate origin node. The surviving nodes then determine which of their own care targets were terminated by the node failure. For each terminated care targets, notifications are sent to the appropriate carers. This allows surviving processes to correctly recover from severed process relationships.

Abstract: A method and apparatus of authenticating and verifying the integrity of software modules is disclosed. In one embodiment, said software modules initially establish their corresponding credentials. Then said local software module ensures its integrity by validating its own digital signature. Said local software module authenticates the integrity of said partner software module after having derived and validated certain information from said partner module's credential. In addition, secure linkage between said local software module and said partner software module is maintained.

Abstract: A CPU in a computer includes a control information management table for storing information about whether an error has occurred in a control unit in the computer or in a control unit in a communications card. When an error occurs in any of the control units, the occurrence of the error is recorded in the control information management table, and an error message is transmitted by the monitor to an operator. When a dump collection command is issued by the operator in response to the error message, the monitor specifies the CPU in the computer or the communications card which operates the control unit where the error has occurred, by referring to the control information management table, and collects only the dump information corresponding to the control unit.

Abstract: A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.

Abstract: The present invention provides a test and diagnosis system for testing an embedded processor. The test system includes an ASIC having an embedded microprocessor, a debug assist logic unit for monitoring the addresses and data from the embedded microprocessor, a debug kernel and an instruction overlay harness. When the debug assist logic block finds a predetermined set of match conditions, it interrupts the embedded microprocessor and transfers control from the code running on the microprocessor to the debug kernel. The debug kernel is coupled to the debug assist logic unit and responsive to user input, the debug kernel allows the user to trace processor transactions during code execution. A REMAP bit in the ASIC allows remapping of the microprocessor memory into a faster instruction overlay memory, allowing the code to be quickly modified during product debug.

Abstract: A disk array controller or a disk array system includes a disk array control unit having an MPU 8 and a user data transfer control unit having host interfaces 3 and 4 with a host computer 17, a memory 5 for temporarily storing data, a redundant data generator 7 for generating redundant data, multi-channel disk device interfaces 16a.about.16e and 12a.about.12e and a data transfer control circuit (DMAC) 6 for controlling the data transfer between the host interface, the memory, the redundant data generator and the disk device interface. Internal buses are of at least three-bus structure including a control bus (for MPU) 15, a host data bus 13 and a drive data bus 14.

Abstract: A method of securely loading and validating commands (COM) in a smart card (SC) is disclosed. Especially in the case where application-specific commands are loaded by an application provider (AP), that is off-line with respect to the card issuer (CI), it must be ensured that the commands are valid. The invention provides a method involving the protection of the commands (COM) by means of authentication codes, these codes (MAC1, MAC2) being produced using two different keys: one key (K1) is stored by the card issuer (CI), the other (K2) by a trusted third party (TTP). A further authentication code (MAC3), produced using a key from a set of keys (K3*), may be utilized to selectively validate commands for individual applications (e.g. AP1, AP2).