Abstract: The present invention is a key conversion system for deterministically and reversibly converting a first key value of a first communications system into a second key value of a second communication system. For example, the key conversion system generates a first intermediate value from at least a portion of the first key value using a first random function. At least a portion of the first intermediate value is provided to a second random function to produce a second value. An exclusive-or is performed on at least a portion of the first key value and at least a portion of the second value to generate a second intermediate value. At least a portion of the second intermediate value is provided to a third random function to produce a third value.

Abstract: A method and system are provided for authenticating users in a client-server system in a way that allows a user to sign-on to numerous servers using a different password for each server, while still only having to remember a single master password. According to one aspect of the invention, a client generates a first set of server-specific authentication information for a first server based on master authentication information stored at the client and data associated with the first server. The client then supplies the first server-specific authentication information to the first server to access restricted resources controlled by the first server. The client generates a second set of second server-specific authentication information for a second server based on the same master authentication information. However, to generate the server-specific authentication information for the second server, the master resource information is combined with data associated with the second server.

Abstract: A system and method of saving a Web page from a Web site on an Internet to a computer-readable medium is disclosed. A Web page is downloaded from the Internet to the computer-readable medium. The Internet address for the Web page is stored on the computer-readable medium. When the Web page is opened from the computer-readable medium, the Internet address is used to identify a security context for the Web page. By using the Internet address to identify the security context for the Web page, the system and method of the present invention allows users to securely view and execute Web pages downloaded from the Internet.

Abstract: A system for predicting failure of a disk is provided. A test string of performance sensitive reads is built and calibrated. That is, the positioning time and spindle speed for each performance sensitive read is logged. The test string is then applied to a disk and the positioning time and spindle speed for each performance sensitive read, as applied, is measured. The calibrated positioning times and spindle speeds are then compared with the measured positioning times and spindle speeds. The comparison result is used as a reliable predictor for disk failure.

Abstract: Interactions among multiple processors (92) are exhaustively tested. A master processor (92) retrieves test information for a set of tests from a test table (148). It then enters a series of embedded loops, with one loop for each of the tested processors (92). A cycle delay count for each of the tested processors (92) is incremented (152, 162, 172) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (176). In each such test (176), the master processor (92) sets up (182) each of the other processors (92) being tested. This setup (182) specifies the delay count and the code for that processor (92) to execute. When each processor (92) is setup (182), it waits (192) for a synchronize interrupt (278). When all processors (92) have been setup (182), the master processor (92) issues (191) the synchronize interrupt signal (276). Each processor (92) then starts traces (193) and delays (194) the specified number of cycles.

Abstract: An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability.

Abstract: Methods, systems and computer program products are provided for error recovery in a network having a first application associated with a first endpoint node and a second application associated with a second endpoint node. These methods, systems and computer program products non-disruptively switch the first application associated with the first endpoint node to a third endpoint node arbitrarily selected from existing endpoint nodes when the first endpoint node is no longer available to the second application associated with the second endpoint node. The first application is provided on the third endpoint node in substantially the same state as the first application existed on the first endpoint node prior to the unavailability of the first endpoint node. The present invention is preferably carried out where the endpoint nodes are VTAM facilities. Also, the first and third endpoint nodes are VTAM facilities in the same SYSPLEX.

Abstract: The detection and elimination of viruses on a computer network is disclosed. An apparatus for detecting and eliminating viruses which may be introduced by messages sent through a postal node of a network electronic mail system includes polling and retrieval modules in communication with the postal node to determine the presence of unscanned messages and to download data associated with them to a node for treatment by a virus analysis and treatment module. A method for detecting and eliminating viruses introduced by an electronic mail system includes polling the postal node for unscanned messages, downloading the messages into a memory of a node, and performing virus detection and analysis at the node.

Abstract: A fault tolerant network interface is achieved by providing primary and alternate network controllers, dual transceivers, dual cables and dual connectors. This fault tolerant interface is driven by a logical device driver which controls the physical device drivers for the primary and alternate network controllers. The logical device driver causes periodically polling messages to be sent between the primary and alternate network controllers to determine if a fault has occurred in either of these network controllers. Faults detected are logged and error recovery actions are provided according to the nature of the faults detected. If the primary network controller is found to be faulty, the secondary network controller will assume the physical address of the primary network controller and provides the services of the primary network controller while the primary network controller is effectively removed from the network.

Abstract: A wide-area computer network system provides bandwidth based on network demand, throughput, and delay requirements, distribution of network load over multiple, parallel connections from the originating node to a destination node, a method of enabling efficient exchange of packet data routing information, modem pooling, an authentication procedure, and a virtual interface as a logical network interface for providing circuit switched connectivity, such as a connection between a host/application and a remote network.

Abstract: A software unit development and test methodology in which a software application or project is dividing into conceptual units. Each unit is first developed and debugged in an isolated testing environment which simulates the actual testing environment through test conditions. Following unit testing, other tested units are incrementally combined and tested in a similar isolated manner. Automatic generation of a testing environment and development system driving debugging and testing software, for measuring testing completeness, and for verifying correctness of future development and maintenance efforts are provided.

Abstract: A system that allows the continuous accessing of data on a floating point processor unit (FPU), by providing two data ports and corresponding buses between the data cache and the FPU. Further, synchronization between the fixed point unit (FXU), which provides the addresses, and the FPU is provided so that data can be loaded in the event of a data cache miss. This synchronization allows data to be transferred from the DCU to the FPU independent of an error condition (cache miss) on one of the buses. If a cache miss occurs that affects a first one of the buses, then the instruction corresponding to this data is held. Subsequent floating point data is received by the FPU on the second bus not subject to the miss. Synchronization signals include, load ready (LD1.sub.-- RDY) indicating to the FPU that data is on the bus and ready to be moved to the FPU and load not ready (LD1.sub.

Abstract: A method decodes a digital information signal which has been coded using a first error correction code and then coded again using a second error correction code. This method comprises the steps of decoding (104) and correcting errors (106) in the coded digital information signal using a decoder corresponding to the second error correction code to produce a first corrected signal. In addition, the method includes the steps of decoding the first corrected signal to obtained position of erasures (108). Next, the erasure location polynomial (112) and modified syndrome components (114) are computed followed by generating an error evaluator polynomial (118) when the modified syndrome components are all zeroes (116). The method also includes the step of calculating error values (120) and correcting errors (122)in the first corrected signal to produce the digital information signal.

Abstract: One or more Central Processing Complexes (CPC), each with one or more programs being executed, become command initiators by issuing commands requesting an action to be performed by a command responder. The responder is a Structured Electronic Storage (SES) which comprises a coupling facility. The SES receives commands to be executed over a plurality of links interconnecting the CPC's and SES, and returns a response to the program that issued the command. The SES is the focal point for the CPC's to share data, control locks, and manipulate lists or queues. This couples the autonomous CPC's into a System Complex (Sysplex) displaying a single system image. An indicator associated with each of the links is set by SES when it appears to a initiator that problems on the link exist. The set state of any indicator prevents SES from starting execution of any subsequent commands.

Abstract: A magnetic recording/reproduction device is disclosed that records data while forming serially a plurality of recording tracks on a magnetic tape. Each of the plurality of recording tracks have a plurality of data blocks recorded of the same bit length. Each of these plurality of data blocks includes a track data indicating the number of the track to be recorded and a synchronizing data indicating a synchronizing signal. The magnetic recording/reproduction device includes circuits for extracting the synchronizing data and the track data from each of the data blocks reproduced immediately after recording, a circuit for counting the number of synchronizing data extracted from the read out data blocks, a circuit for detecting a time period interval of synchronizing data for each recording track, a circuit for extracting track data from the read out data blocks, and a circuit for comparing the extracted track data with an expected data for each recording track.

Abstract: A memory which is cleared by simultaneously clearing a special bit in each entry within the memory, an extra bit, used for other purposes, is also cleared. When both bits have a value of 0, parity checking is disabled. When either bit has a value of 1, parity checking is enabled. This prevents incorrect detection of parity errors after the memory device has been cleared.

Abstract: An abnormal message detecting and processing apparatus comprises an example message storing part (30) for storing examples of normal messages, a variable field information storing part (32) for storing information of a location of variable fields in the example messages, and an abnormal message detecting part (34). The abnormal message detecting part (34) compares input messages (36) with the example messages, except for variable fields specified by the information stored in the variable field information storing part (32), determines that an input message is abnormal if none of the example messages coincide with the input message in the comparison, and outputs the message so that the abnormal message is easily distinguishable from normal messages.