Abstract: A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.
Type:
Grant
Filed:
January 3, 1989
Date of Patent:
October 30, 1990
Assignee:
Siemens Aktiengesellschaft
Inventors:
Lothar Risch, Reinhard Tielert, Wolfgang Mueller, Christoph Werner
Abstract: The present invention constitutes an improvement of the Local Encroachment Reduction (LER) process developed by Tyler Lowrey at Micron Technology, Inc. of Boise, Idaho. LER consists of selectively etching a portion of the field oxide which has encroached into a DRAM cell's active area and then subjecting the cell to a high-energy boron implant to maintain adequate active area isolation. Although the boron implant effectively decreases the width of the depletion region between n+ active areas and p+ substrate, it has the undesirable effect of reducing the breakdown voltage at the n-p junctions in the bird's beak regions at the edges of the active regions, thus increasing the cell's susceptibility to gated-diode breakdown following creation of the cell plate. The present invention solves this problem by creating a graded junction in the bird's beak regions of the cell. The graded junction reduces the electric field intensity in the junction region, resulting in an increase in the breakdown voltage.
Abstract: Isolation trenches are formed in a semiconductor, e.g. silicon, substrate by selectively doping the substrate and preferentially oxidizing the doped material. Typically the dopant is arsenic or phosphorus and preferably the substrate is doped to a level of at least 5.times.10.sup.19 cm.sup.-3.
Type:
Grant
Filed:
September 21, 1989
Date of Patent:
September 18, 1990
Assignee:
STC PLC
Inventors:
Sureshchandra M. Ojha, Paul J. Rosser, Philip B. Moynagh
Abstract: Smut may be removed from the surface of aluminum or aluminum alloys by a deoxidizer comprising nitric acid, a halate salt, and, optionally, an activator.