Abstract: To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

Abstract: A method for fabricating a semiconductor device comprises implantating and diffusing a first well in a semiconductor substrate. A second well is implantated and diffused in the first well. A third well is implantated in the second well and a MOS transistor is formed in the third well.

Abstract: A GaN type semiconductor layer having a new structure is provided which incorporates a substrate having surface which is opposite to a GaN type semiconductor layer and which is made of Ti.

Abstract: A method and structure for implementing dynamic burn-in of semi-conductor chips in TAB processing is provided. The semi-conductor chips are mounted on a wire pattern formed on the obverse side of an insulating tape in a conventional way. The insulating tape has a plurality of openings extending therethrough, one opening between each adjacent location of a chip. Wires from the wiring pattern at each chip location pass over the openings on the obverse side of the tape. A second insulating tape is provided which has a series of parallel conductors formed on one surface thereof. The spacing of the conductors corresponds to the spacing of the wires over the openings.The second tape is applied to the reverse surface of the first tape with the conductors on the second tape in registration with the wires over the openings in the first tape and the wires are electrically bonded to the conductors. Thus, various voltage and signal levels can be supplied for all of the chips simultaneously during dynamic burn-in.