Abstract: A method of forming a bipolar transistor. A base region is implanted into an epitaxial layer. An emitter and collector contact regions are formed of doped polysilicon on the epitaxial layer, the emitter being formed over the base region. The implant is below the surface of the epitaxial layer in all regions not covered by the collector region. Low resistance silicide contacts, such as titanium or cobalt, are formed on the structure in a self-aligned fashion. This method is well suited for forming BJTs as part of BiCMOS circuits.

Abstract: A reusable semiconductor package such as a ceramic pin grid array package is described. The package includes a housing having a bottom wall for supporting a semiconductor die. The housing defines therein a cavity which is open at the top and which communicates with the environment through a hole in the bottom wall. A disposable base suitable for supporting a semiconductor chip is adapted to be placed on top of the bottom wall. The base covers the hole entirely when it is used to support the chip. The base is then sealingly attached to the housing in a manner that it can be removed from the housing without any substantial damage to the housing. When the package is to be reused for a different chip, the base can be easily removed by applying a force through the hole through the bottom wall. The original die and base may be simply disposed and a new die on a new base be put in their place.

Abstract: A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: Disclosed is a semiconductor memory device (DRAM) which includes a plurality of island regions, at least one cell transistor disposed on each island region and cylindrical capacitor surrounding said each island region. By so composing, the capacity of the cell capacitor incorporated into a small space can be increased.Also disclosed is method of fabricating a semiconductor memory device which includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane excelling in coverage on it, a step of etching by an etching method having a strong anisotropy in the vertical direction while leaving said deposit membrane on sidewall, and a step of etching deeper the exposed portion of the semiconductor surface in the groove and forming capacity element and isolation region by using this deep trench.