Abstract: The present invention discloses an array substrate and a manufacturing method thereof, and a display device, the array substrate includes a pixel electrode and a thin film transistor, the pixel electrode includes a first sub-electrode, a first connection part formed integrally with the first sub-electrode, a second sub-electrode, and a second connection part formed integrally with the second sub-electrode, the first sub-electrode and the second sub-electrode are insulated from each other and are disposed in different layers, and both the first connection part and the second connection part are connected to a drain of the thin film transistor. With the present invention, the pixel electrode of the discrete pattern structure can be manufactured to have a narrow gap smaller than the resolution of the exposure machine, to solve the problem that the single-layered pixel electrode of the discrete pattern structure cannot be resolved by the existing exposure machine.

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

Abstract: Examples are provided that describe a model free power detector. In one example, a method includes receiving, by one or more computing devices, a measurement of electrical power to a robotic device. The method also includes receiving, by the one or more computing devices, a measurement of mechanical power by the robotic device. Based on combinations of the electrical power to the robotic device being one of positive, negative, or about zero, and the mechanical power by the robotic device being one of positive, negative, or about zero, the method includes determining possible states of operation of the robotic device. The method also includes providing, by the one or more computing devices, the possible states of operation of the robotic device to a detector.

Abstract: A metal oxide semiconductor varactor includes an active area doped well that is disposed within a semiconductor substrate and a gate structure including a first portion that extends over the active area doped well and a second portion that extends over the semiconductor substrate outside of the active area doped well. The varactor further includes at least one active area contact structure formed in physical and electrical connection with the active area doped well, in a three-sided contact-landing area of the active area doped well. Still further, the varactor includes a gate contact structure that is formed in physical and electrical contact with the gate structure in the second portion of the gate structure such that the gate contact structure overlies the semiconductor substrate outside of the active area doped well.

Abstract: The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one side surface of the facing bar; forming a bit line plug that is electrically connected to one side of the transmission channel, which is formed on the one side surface of the facing bar; and forming the storage that is electrically connected to the other side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate. A pair of DRAM cells shares a facing bar and a bit line plug. In accordance with the present disclosure, a required layout area is significantly reduced.

Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.

Abstract: This method for manufacturing a silicon wafer includes: a first heat treatment step of performing RTP treatment on the silicon wafer in an oxidizing atmosphere; a step of removing a region in the silicon wafer in which an oxygen concentration increases in the first heat treatment step; a second heat treatment step of performing, after performing this removing step, RTP treatment on the silicon wafer in a nitriding atmosphere or an Ar atmosphere; and a step of removing, after performing the second heat treatment step, a region in the silicon wafer in which an oxygen concentration decreases in the second heat treatment step. This method enables the manufacture of a silicon wafer in which latent defects such as OSF nuclei and oxygen precipitate nuclei existing in a PV region are destroyed or reduced, and that has a gettering site.

Abstract: A method for partially filling an open feature on a substrate includes receiving a substrate having a layer with at least one open feature formed therein, wherein the open feature penetrates into the layer from an upper surface and includes sidewalls extending to a bottom of the open feature. The open feature is overfilled with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature. The method further includes removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature, and converting the chemical composition of the organic coating plug to create an inorganic plug.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.

Abstract: A packaging method, a display panel, and a display apparatus. The packaging method comprises steps of: forming a frit layer in a packaging area of a first substrate; forming at least a metal thin film and/or at least a silicon thin film on the frit layer formed on the first substrate, and forming at least a metal thin film and/or at least a silicon thin film in a packaging area of a second substrate, wherein one of the outermost thin film formed on the frit layer and the outermost thin film formed is a metal thin film, and the other is a silicon thin film; and vacuum laminating the first substrate and the second substrate, without the use of a laser to irradiate the frit layer during the packaging.

Abstract: An integrated and rigless method of determining the location and the type of damage in casing or tubing of a wellbore that involves recording a thickness profile of the casing or tubing, a temperature log, and a noise log along the depth of the wellbore, followed by locating the damage from the thickness profile, and determining the type of damage from the temperature log and the noise log.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

Abstract: Provided is a method of manufacturing an epitaxial wafer having an excellent gettering capability while suppressing formation of epitaxial defects. The method includes: a cluster ion irradiation step of irradiating a surface of a silicon wafer having a resistivity of from 0.001 ?·cm to 0.1 ?·cm with cluster ions containing at least carbon at a dose of from 2.0×1014/cm2 to 1.0×1016/cm2 to form, on a surface portion of the silicon wafer, a modifying layer composed of a constituent element of the cluster ions in the form of a solid solution; and an epitaxial layer forming step of forming, on the modifying layer on the silicon wafer, an epitaxial layer having a resistivity that is higher than the resistivity of the silicon wafer.

Abstract: In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.

Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.

Abstract: An LED package structure includes a conductive frame assembly, a reflective housing, an UV LED chip disposed on the conductive frame assembly, and a die-attach adhesive for bonding the UV LED chip to the conductive frame assembly. The reflective housing includes Silicone Molding Compound (SMC) and filler mixed in the SMC. The energy gap of the filler is greater than or equal to 4 eV. The energy gap of the filler thereof can be chosen by the following formulas. When the refractive index difference between the filler and the SMC is less than or equal to 0.2, the energy gap of the filler is satisfied the following formula. E?1240 (nm·eV)/(??150(nm)). When the refractive index difference between the filler and the SMC is greater than 0.2, the energy gap of the filler is satisfied the following formula. E?1240(nm·eV)/(??50(nm)).

Abstract: The microintegrated sensor comprises a stack formed by a sensor layer, of semiconductor material, by a cap layer, of semiconductor material, and by an insulating layer. The sensor layer and the cap layer have a respective peripheral portion surrounding a central portion, and the insulating layer extends between the peripheral portions of the sensor layer and of the cap layer. An air gap extends between the central portions of the sensor layer and of the protection layer. A through trench extends into the central portion of the sensor layer as far as the air gap and surrounds a platform housing a sensitive element. The cap layer has through holes in the insulating layer that extend from the air gap and form a fluidic path with the air gap and the through trench.

Abstract: The present invention provides a phosphor with a preferred orientation represented by the following formula: A2[MF6]:Mn4+, wherein A is selected from a group consisting of Li, Na, K, Rb, Cs, and NH4, M is selected from a group consisting of Ge, Si, Sn, Ti, and Zr. The preferred orientation is a (001)/(011) preferred orientation. The present invention also provides a method for fabricating the above phosphor. The present invention further provides a light-emitting element package structure employing the same.

Abstract: A display apparatus includes a substrate, an emission layer on the substrate; a planarization layer between the substrate and the emission layer; and a thin-film transistor between the substrate and the planarization layer. The emission layer includes a light-emitting diode (“LED”) electrically connected to the thin-film transistor, and a pixel separation member which surrounds the LED and is in contact with side surfaces of the LED.