Abstract: A reconfigurable processor includes at least three (3) MacroSequencers (10)-(16) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (18) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (20) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (66) is provided having an input for receiving at least one external output and at least the feedback path.

Abstract: A master isochronous clock structure wherein a frame-rate clock of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clocks signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data. In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data.

Abstract: An apparatus and method for transparent on-the-fly decompression of the program instruction stream of a processor. Connected between a processor and a memory storing compressed information is a decompression device. The decompression device, receives a request from the processor for information, retrieves compressed information from the memory, decompresses the retrieved compressed information to form uncompressed information, and transmits the uncompressed information to the processor. The compressed information may include both program instructions and data. When the decompression device receives a request for information, which includes an unmodified address, from the processor, it generates an index offset from the received unmodified address. An indexed address corresponding to the generated index offset is retrieved from an index table. Compressed information corresponding to the selected indexed address is retrieved from the memory and transmitted to the processor.

Abstract: A system, method and medium for configuring an item such as a machine having multiple optional components is provided. This is accomplished using “options,” which correspond to the optional components of the machine, and are selected by a user according to those optional components that the user desires to have as part of the machine. Each option is envisioned to be created to contain the necessary properties (such as attributes and constraints) to appropriately configure the corresponding optional component within the machine. Embodiments of the present invention envision that the options can be arranged in a hierarchical option tree to help allow a user to better visualize the structure of the machine in making decisions concerning configuration.

Abstract: A computer system device includes a data bus that transmits a plurality of bits of data, and a strobe line. The computer system device further includes a strobe signal generator that generates a strobe signal, and a variable delay device that couples the strobe signal generator to the strobe line. The variable delay device selectively delays the strobe signal.

Abstract: A computer recovery system provided on a removable high capacity disk. In the event that a user encounters an abnormal operating condition, the user inserts the removable high capacity disk into the computer and restarts the computer. The computer boots either directly from the removable high capacity disk or from a floppy disk which transfers control to the removable high capacity disk. The removable high capacity disk includes all of the files necessary to load the computer operating system and launch the graphical user interface of the operating system such that the user is provided with a familiar operating environment. The removable high capacity disk also includes a suite of software recovery software which attempt to ascertain and correct the cause of the abnormal operating condition to return the computer system to a normal operating condition.

Abstract: A personal authentication system provides at least two levels of security for an authentication process, in addition to numerous other security features. The system operates across many different software and hardware platforms, in a client/server fashion, employing a challenge/response process that does not require users to transmit their passwords across a network. An application running on a client computer is coupled with an application running on a server computer. The client generates a response to a challenge, which is provided by the server. The response is a combined function of the server's challenge, a serial number assigned to the client, and a password provided by the user.

Abstract: A system software solution for controlling an enterprise which defines and illustrates the electrical, pneumatic, hydraulic, logic, diagnostics, external behavior, controlled resources and safety elements of an enterprise control system. The elements of the control system are encapsulated in objects of an object-oriented framework within a control assembly. The control assembly is the fundamental building block for providing object-oriented control of the enterprise. A control assembly component is a deployable control subsystem that provides an interface using a common object model that is configurable. The enterprise control system is used to define user interfaces including sequence charts that are updated in a substantially realtime manner utilizing the control assemblies associated with the generated code for the enterprise control system.

Abstract: The invention relates to a multi-output monolithic device, and particularly to a multi-output monolithic integrated circuit device without generating a simultaneous switch output (SSO) in communication or in a network, in which the plurality of output port will not switch from "0" to "1" or from "1" to "0" simultaneously to prevent insufficient power supply caused by a simultaneous switch, resulting in noise generation and errorous operations. A multi-bit shift register in used in the invention to make each output port have a different and to reduce the probability of the same output value on each output port, thereby reducing the influence of SSO. Then, a slightly different delay is made of each output port during output, so as to eliminate SSO.

Abstract: In a debugging system for use in realizing simultaneously complete observation of internal operation and reproduction of malfunction actually caused in a target system which includes an integrated circuit, such as a microprocessor, contents of a memory and an internal initial state of the target system are snooped and stored in a snoop unit and a trace memory, respectively, both of which are included in a probe unit attached to the target system. The internal operation and the reproduction are simulated by a software simulator model by the use of the contents and the internal initial state which are stored in the trace memory and which are sent from the probe unit.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A system having a bus coupled to a host and a peripheral controller device each coupled to a bus. The bus includes a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device communicates with the host over the bus to control devices such as parallel port controllers, serial port controllers, super I/O controllers, floppy disk controllers, keyboard controllers and memory devices.

Abstract: A computer system that implements communication support with a minimum amount of main memory. The computer system provides a Basic Input/Output System (BIOS) for execution in Random Access Memory (RAM). Included in the BIOS is the communication initialization and runtime code. Upon initialization, the communication initialization code is executed, configuring and initializing communication devices, including a Universal Serial Bus (USB) device. After the initialization, the runtime communication code is moved to a secure memory, such as System Management Mode (SMM) memory. The runtime communication code is executed in response to an interrupt to the secure memory. If the secure memory is SMM memory, then a SMI will trigger the execution of the communication code. The main memory is not accessed to execute the runtime communication code.

Abstract: An intelligent network agent software application for multi-segment network devices (such as bridges or multi-segment repeaters) which have one or more network links automatically configures the network links. Several automatic configuration and loop-recovery features are encompassed, each of which applies toward intelligently making decisions on the user's behalf, without special knowledge or intervention on the part of the user. Such configuration includes: assigning bridged links to different segments (to maximize the connectivity offered by the bridging and to prevent looping); setting up bridged links on a bridge to form full connectivity across the network with another bridge; setting up redundant connections; disabling ports which are causing loops in the network, or other configuration actions. The agent is preferably fully embedded in the hardware device.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: A method for distributing synchronization in an optical communications network is disclosed. In order to keep costs to a minimum, the method consists of deploying requisite primary reference source (PRS) clocks only at those sites having access to more or less than two independent synchronization distribution paths (SDPs). PRS clocks are also preferably installed at sites located substantially far from a site already equipped with a PRS clock. As a result, a small number of PRS clocks end up being installed, leading to substantial cost savings for the telecommunications service provider. Subsequently, a building integrated timing supply (BITS) system is deployed at all sites comprising more than one network element. The BITS has two timing inputs, a primary and a secondary timing reference, selected from two of the accessible SDPs.

Abstract: An improved transceiver that is tightly integrated into an enhanced receiving chip for a computer monitor. The transceiver includes a receiver having a first input port for receiving serialized data, a first output port for transmitting deserialized data to the transceiver, and a second input port adapted for receiving feedback data forwarded from a sensor to an audio and video control unit. The serialized data comprises video, audio and control data. The transceiver further comprises a receiver operably coupled between the first input port and the first output port, as well as a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. The transceiver also includes a transmitter with a third input port for receiving parallel data and a second output port for transmitting a serial data stream. The parallel data are received by the third input port concurrently with the serialized data being received by the first input port.

Abstract: An apparatus for setting up a time/date of a CMOS real-time-clock within a computer system is disclosed. The computer system includes a processor, a memory, an I/O controller and a first parallel port interface. The apparatus uses the first parallel port within the system to set up the CMOS real-time-clock. The apparatus includes a reference real-time-clock for storing a reference date/time, a second parallel port interface connected to the first parallel port interface. The second parallel port interface is connected to the reference real-time-clock through a signal line. The computer system, responsive to a set-up instruction, reads the reference date/time from the reference real-time-clock and writes the reference date/time, via the I/O controller, into the CMOS real-time-clock of the computer system.

Abstract: A Local Register Network (LRN) includes multiple nodes connected together by a local register bus. The nodes each include logic circuitry, one or more configuration registers, a data path and a decoder. The local register bus is unidirectional and transfer data and addresses to each one of the nodes. The decoder in each node contains local memory maps for the node configuration registers. Each decoder determines whether an address on the local register bus maps to the associated configuration registers and whether the accessed configuration registers read data onto the local register bus or write data from the local register bus. If the address does not map to the node, the data path passes the data to the next node in the LRN network.

Abstract: A clock signal generator within an electronic device locally generates a reference clock signal having a reference frequency from a base clock signal having a base frequency. The base clock signal is from a base signal source that is external to the electronic device, and the base frequency of the base clock signal may vary depending on the base signal source. The present invention includes a plurality of frequency dividers which are coupled to the base signal source. Each of the frequency dividers outputs a divided clock signal having a respective frequency that is the base frequency divided by a respective factor. A multiplexer accepts the value of the base frequency of the base clock signal as stored within a storage device that is external to the electronic device. The multiplexer then selects as the reference clock signal a divided clock signal having a respective frequency that is closest to the reference frequency depending on the value of the base frequency.