Abstract: A method is disclosed for coordinating membership subject to an asymmetric safety condition from multiple processes in a distributed system. Each is callable by a distributed application for system status or for executing tasks of the application. Initially, each process sends the other processes its view on their status, where the view includes the names of a group of the processes. It then waits for similar views from other processors except those regarded as failed in its own view, up to a predetermined timeout. Each process then generates a resulting view by intersecting its local view with the names of those processes from which it has received views. The local views are updated based on the resulting views and again exchanged until a termination condition occurs.

Abstract: In a Plug and Play environment different kinds of EEPROMs can be used having different access protocols without having to add an additional pin to the EEPROM to indicate its type. The first type of EEPROM has a code which indicates the first type stored on a predetermined address whereas the second type of EEPROM having a different read protocol has another code which indicates the second type stored on a consecutive address. When the Plug and Play controller accesses the EEPROM for a read either the code 1 or code 2 is outputted whereby the appropriate read protocol is identified.

Abstract: A poly-phase filter and an apparatus which compensates for timing error and a method for implementing such compensation are provided. The poly-phase filter can compensate for the timing and phase error of an input signal which occur in a time period which is shorter than the sampling period by obtaining impulse responses of a mother filter having a pass band of (Fs/2n) where Fs is the sampling frequency and n is a positive number, re-sampling the obtained impulse responses using a plurality of clock signals having a phase difference of (2*.pi./n s), and selecting one filter among the filter set having group delays corresponding to the detected phase, and filtering the input signal using the poly-phase filter constituted by a series of filter sets adopting the re-sampled respective impulse responses as transmitting characteristics of the element filters.

Abstract: A house is two-dimensionally moved, and generates first and second analog signals representative of a movement in opposing first and second directions and another movement in opposing third and fourth directions that are perpendicular to the first and second directions. A data input device compares the first and second analog signals with a periodically changing reference signal to output a first pulse signal and a second pulse signal depending upon the comparison result, and selectively transfers a first pulse train and a second pulse train depending upon the duty factors of the first and second pulse signals so as to generate a composite digital signal representative of the motion of the mouse to a computer unit.

Abstract: A protocol control circuit for transferring data conforms to the IEEE 1394 standard. The control circuit includes a decoder and RS-type flip-flops.

Abstract: A filtering method and apparatus in which an input signal is subjected to an analog filtering step, then an analog to digital conversion step and finally a digital filtering step to produce a filtered output signal. The pulse response of the digital filter is the mirror image of the pulse response of the analog filter and the cascaded filtering steps result in a filtered output signal which exhibits little or no group delay or phase distortion. The digital filter may be a FIR filter. Also disclosed is a phase error correction method whereby a pulse is inserted into a circuit or data stream prior to a group delay imparting device or function, a pulse response of the group delay imparting device or function is measured prior to a phase correcting device or function, mirror image filter coefficients are calculated using a window function and then incorporated into a phase correcting filter arrangement.

Abstract: A system and method for a target computer to use a storage device of its host computer and in particular for bootstrapping an operating system from the storage device onto the target computer. The computer system comprises a host computer coupled to a target computer via an I/O bus. In one embodiment the target computer is an embedded system comprising an intelligent data acquisition device. The host computer includes a disk drive with a file system and a file which serves as a virtual disk drive for the target computer, i.e., the file is essentially an image of a disk drive which would otherwise be coupled to the target computer. The target computer may be a BIOS level IBM-compatible personal computer. The target computer includes an option ROM with an int13H handler which hooks the disk service routine software interrupt vector of the target computer and forwards INT 13H requests to a device driver executing on the host computer via a shared memory on the target computer.

Abstract: The present invention relates to a fast calculation method and, more particularly, to a fast calculation method and its hardware apparatus using a linear interpolation operation. Primarily, the two existing values of the two given points X and Y intended to proceed the linear interpolation operation are stored in two registers A and B respectively, and then they are added through an adder and the lowest order bit of the sum is discarded to form a mean value. The resulting value discarded from the lowest order bit is then sent to a multiplexer and every bit in the binary representation of the position pointer K is sent to a selection input terminal of the multiplexer in sequence from the highest order bit to the lowest order bit. The resulting value discarded from the lowest order bit is sent back to either one of the two registers A and B in accordance with the digit of the corresponding bit in the binary representation of the position pointer K.

Abstract: The block based data storage subsystem combines the functions of data storage/retrieval with block based data management functions, including but not limited to: Hierarchical Storage Management (HSM), Live Data Backup, Fault Tolerance, Capacity Planning, Performance Optimization and Dynamic Load Balancing. This system solves many storage management problems with a single technology and is completely independent from, and non intrusive to, the system it attaches to and has resources specifically designed to perform data management functions. The perspective of block data management is a much finer granularity and much simpler than existing data file based technologies.

Abstract: An improved full subtracter is disclosed which receives a minuend signal A having a weight of +1, a subtrahend signal B having a weight of -1 and a borrow input signal Xi having a weight of -1 and provides a difference output: signal D having a weight of +1 and a borrow output signal Xo having a weight of -2. The full subtracter is composed of CMOS transistors such that both the signal D delay time and the signal Xo delay time are decreased by reducing the number of logic gate stages.

Abstract: A partial product adder for summing up four partial products P0, P1, P2, and P3 which are binary numbers in twos-complement representation having different weights is composed of a carry save adder consisting of an array of 4:2 compressors each having four inputs. Of the four inputs of each 4:2 compressor, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths. To implement sign extension of the first partial product P0 having the smallest weight, a logic circuit provides, in a plurality of digit positions higher than the sign digit P0s of the first partial product, values resulting from a logic operation between the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product having the second smallest weight.