Abstract: A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.