Abstract: A method and system for providing a timed power-on of logical partitions in a logical partition computer system is disclosed. An operator is allowed to enter a timed power-on value (TPO) value representing a time to boot one or more of the logical partitions. The TPO value for each of the logical partitions is then stored in nonvolatile memory. The system time is then periodically compared with each of the TPO values, and the corresponding partition is booted when the system time is greater than or equal to the TPO value.

Abstract: A device for recognizing functional units in an electrical system, which is one of being optional and provided in different construction stages, respectively, comprising a data processing unit and at least one functional unit, the functional unit having a function register with a nonvolatile memory for holding function data, the memory having at least one function entry with function data associated with the physical properties of the functional unit, a change in the properties of the functional unit being recordable by changing the corresponding function data of the function entry in the function register; and a method of operating the device.

Abstract: A method of reading configuration ROM in a serial bus device reads only portions of the ROM that are organized in a directory structure. Typically, the configuration ROM follows the IEEE 1212 and/or 1394 standards and uses an IEEE 1394 bus. Based on the information read from the configuration ROM, a connecting computer can determine the appropriate device driver to use for communications with the device.

Abstract: An electronic device includes an external supply voltage terminal and a circuit. The circuit provides an indication of a first supply voltage level to be furnished to the supply voltage terminal in response to receiving power from the terminal.

Abstract: A method, apparatus, and computer implemented instructions for controlling power in a data processing system having a plurality of logical partitions. Responsive to receiving a request to turn off the power for a logical partition within the plurality of logical partitions in the data processing system, a determination is made as to whether an additional partition within the plurality of logical partitions is present in the data processing system. The power is turned off in the data processing system in response to a determination an additional partition within the plurality of logical partitions is absent in the data processing system. The logical partition is shut down in response to a determination that an additional partition within the plurality of logical partitions is present in the data processing system. The mechanism of the present invention also provides for rebooting logical partitions. A request is received to reboot a logical partition within the plurality of logical partitions.

Abstract: It is an object to provide a data terminal which can give a surplus for switching a power supply to an AC adapter and continuing communication without exerting an adverse influence on the server side when a battery voltage of a data terminal drops to the user. To accomplish this object, a microcomputer in an adapter connected to a communication network via a cellular phone or PHS discriminates an operating mode of the adapter when the low-power voltage is detected by an interruption signal from a power supply during the connection of communication with an image server connected to the communication network. While data from the image server is being received or the received data is being printed, the microcomputer waits for seconds while expecting a recovery of the power voltage. If the power supply is exchanged to a new battery or the AC adapter is inserted by the operator during this period of time, the printing operation is resumed.

Abstract: A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.

Abstract: For the tradeoffs between a lower consumption power of a microprocessor and its process speed, a plurality of clocks and power supply voltages are supplied to each of functional units 104 to 107 and a clock switching circuit and a power switching circuit are provided in each of the functional units. When a program mainly using a particular functional unit, e.g., FPU 106, is executed, the operation speed of FPU 106 is raised more than that in a normal operation mode. To this end, a consumption power control circuit 102 supplies a power/clock switching signal 113c to FPU 106. This power/clock switching signal 113c instructs to raise the clock frequency and power supply voltage to be used by FPU 106. In order to compensate for an increase in the consumption power to be caused by the high speed operation of FPU 106, the consumption power control circuit 102 also supplies a power/clock signal 113b to another functional unit, e.g., CPU 105.

Abstract: A plurality of modules are connected in a series and addresses are automatically assigned to the modules upon the application of power. At that time, a module sends a signal to all of the other modules which causes a first timer to be started in each module. After a predefined period, an initial module, at one end of the series, sends a timing signal to the next module in the series. Each module upon receiving a timing signal starts a second timer, delays for the predefined period, and then sends a timing signal to the next module in the series. When terminal module at the opposite end of the series receives a timing signal, that module sends a second signal to all of the modules which causes the modules to stop all of the first and second timers. Each module then uses the values of its respective timers to derive a unique address.