Abstract: A high performance computer system with a plurality of processors and memory modules is arranged with the processor modules stacked one upon the other with first switch modules in a first stack and with the memory modules stacked one on the other with second switch modules in a second stack. The first and second stacks are arranged adjacent to each other with the first and second switch modules diagonally opposed. Interconnecting bus lines couple the processors to the memory modules through the first switch modules and couple the memory modules back to the processors through the second switch modules. The flow of data is in one direction through the memory modules and switches to reduce wire length, latency and skew while supporting fast cycle time and high bandwidth.