Patents Examined by P. M. Chung
  • Reduced delay circuits for shift register latch scan strings
    Patent number: 5150366
    Abstract: Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.
    Type: Grant
    Filed: August 1, 1990
    Date of Patent: September 22, 1992
    Assignee: International Business Machines Corp.
    Inventors: Paul H. Bardell, Jr., William H. McAnney