Abstract: A method of performing a sliding window search includes the steps of: (a) creating an associative database of a plurality of data strings; (b) receiving a first window of a data block; (c) iconizing the first window of the data block to form a first icon; (d) determining if the first icon has a match in the associative database; (e) determining a first byte icon of a first byte of data in the first window; (f) executing an icon shift function to form a shifted first byte icon; (g) exclusive ORing the shifted first byte icon with the first icon to form a seed icon; (h) determining a second icon for a second window using the seed icon and transforming a new byte of data onto the seed icon; and (i) determining if the second icon has a match in the associative database.

Abstract: A software performance analyzer nonintrusively measures six different aspects of software execution. These include histograms or a table indicating the degree of memory activity within a collection of specified address ranges, or indicating the amount of memory or bus activity caused by the execution of programming fetched from within a collection of specified ranges, or indicating for a specified program the relative frequency with which it actually executes in specified lengths of time, or indicating for a specified program the relative frequency of a collection of specified available potential execution times (i.e., the complement of the previous measurement), or indicating for two specified programs the relative frequency of a specified collection time intervals between the end of one of the programs and the start of the other, or lastly, indicating the number of transitions between selected pair of programs.

Abstract: Data is communicated between redundant channels formatted in blocks having an initial command word followed by a destination code, starting address and a variable number of data words including a word count. The blocks are transmitted between each channel and all of the channels over cross-channel data links, each channel receiving the data blocks and determining the validity thereof by counting the number of data words received and comparing that number to the word count transmitted for that block. An interrupt signal indicative of invalidity of a block is provided in the event of a miscompare. A stop address is generated for each block received for storage at the start address. A memory address is generated for each valid word received for storage in sequence starting immediately after the start address. The next block received has its start address placed immediately at the end of the previously received block.

Abstract: The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed.

Abstract: A file backup system for POS data includes a master terminal and a backup terminal along with a master file and a backup file, all of which are coupled to a plurality of satellite terminals. A file controller is provided for each of the files. When one of the files is down, the master file is capable of copying the contents of the down file while simultaneously responding to a request from any terminal and controlling the transfer of data without stopping the operation of the system.

Abstract: A computer is provided as an add-on processor for attachment to a host computer. Included are a single data bus, a 32-bit arithmetic logic unit, a data stack, a return stack, a main program memory, data registers, program memory addressing logic, micro-program memory, and a micro-instruction register. Each machine instruction contains an opcode as well as a next address field and subroutine call/return or unconditional branching information. The return address stack, memory addressing logic, program memory, and microcoded control logic are separated from the data bus to provide simultaneous data operations with program control flow processing and instruction fetching and decoding. Subroutine calls, subroutine returns, and unconditional branches are processed with a zero execution time cost. Program memory may be written as either bytes or full words without read/modify/write operations.

Abstract: A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place.

Abstract: A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.

Abstract: A decompiler for industrial controllers operates on ladder logic programs that have been compiled into series jump format machine code. Series jump machine code evaluates ladder logic rungs through jump instructions jumping to a COIL ON routine, a COIL OFF routine, or another jump instruction, where each contact of the rung is associated with a single jump instruction. The decompiler creates a matrix of connection nodes then simplifies the matrix to return the ladder logic program. A decompiled ladder diagram may be thereby produced without the need for non-executable source code "tokens" included within the compiled machine language program.

Abstract: A memory cartridge is loaded in a main unit of a personal computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Storage area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with progress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits.

Abstract: A memory cartridge is loaded in a main unit of a personal computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Storage area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with progress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits.

Abstract: Instructions in the processor idle loop are used to measure the percentage of time the processor is at idle. The processor idle loop instructions control the processor to alternate a processor data output between output states. The processor data output thus alternates between states whenever the processor is idle, and remains in the same state when the processor is performing useful tasks. A frequency counter or other indicating device responsive to the rate of processor data output state change directly indicates the amount of time the processor is idle relative to the total amount of processing time. Since the change of state, not the state itself, of the data output is detected, it does not matter what state the data output is left in when the processor is interrupted from performing the idle loop instructions.

Abstract: A high-speed input module for a programmable controller has two sensor inputs, one for receiving an indication of a sensed event and another or receiving an indication as to whether the count of such events should be incremented or decremented. Each input is coupled to a separate data latch which temporarily stores the respective indication. The output of the sensed event latch is connected to an interrupt line of the programmable controller. A shift register has a separate parallel input connected to the output of each latch and has a serial output for connection to a data input terminal of the programmable controller. The shift register transfers the sensed indications to the controller in response to clock signals received from the programmable controller.