Abstract: A set of Unique Input/Output Sequence (UIO) Sets is identified for Finite State Machine (FSM) model (33) states. Each member of the Sets of UIO Sets is a UIO Set (63) which are sets of Input/Output (I/O) Sequences that each uniquely identifies FSM (33) states. FSM (33) state transitions are Edges-Under-Test (EUT). A Test Subsequence is constructed for each member of each UIO Set (63) selected for each EUT that includes the UIO Set member and the corresponding EUT. A Test Subsequence (TS) Graph (65) is constructed from the Test Subsequences by connecting Test Subsequence starting and ending states. A Verification Test Sequence for testing a Machine Under Test (14) for conformance with a FSM model (33) is constructed by touring the TS Graph (65).

Abstract: The test apparatus (PC,KB,DIS,PR,IF) communicates via a standard serial bus (12) with a device under test (DUT) to verify conformity with a standard application protocol defining the format, meaning and applicability of messages passed via the bus (12). The apparatus generates a test sequence of commands and requests and analyses the replies of the DUT for conformity. The test sequence and the analysis are adapted automatically in response to previous replies of the device, to provide a thorough but efficient test of the device and any subdevices identified within it. Where the standard application protocol defines extended autonomous cooperation between devices, the test apparatus emulates one or more further devices to be controlled and interrogated by the device under test.

Abstract: A method used by an electronic design automation system for partitioning the logic design of an integrated circuit and generating test patterns for testing the integrated circuit. The logic design of the integrated circuit includes a gate-level description having components and nets. Nets include base nets input to the integrated circuit and apex nets output from the integrated circuit. The nets are specified by vector net notation. The method includes creating a plurality of cones of logic design from the logic design of the integrated circuit. Each cone is defined by tracing a path from an apex net, defined by a logic designer, output from a logical register of the logic design to a logic designer-defined base net affecting the logical register. A test pattern is then automatically generated for each of the traced cones of logic design.

Abstract: A fault-tolerant bridge/router ("brouter") with a distributed switch-over mechanism of the present invention can tolerate any single failures and does not rely on network reconfiguration (or alternative paths) and, therefore, substantially improves system reliability/availability. The fault-tolerant brouter utilizes a plurality of processing elements communicating through a multiple-bus switching fabric. Each processing element can effectively support two ports, each port providing an interface to an individual LAN. Each LAN is then linked to two different ports on two different processing elements, respectively, thereby providing processing element redundancy. If a processing element fails, bridging/routing functions can be performed by the other, redundant processing element. The functions are switched using the switch-over mechanism. Because the switch-over mechanism is distributed, no centralized control mechanism is required.

Abstract: In a spacecraft having devices which are operative in plural modes, particularly an earth sensor operative in a north hemispherical inhibit mode, a south hemispherical inhibit mode, and a normal mode, a watchdog circuit* is employed to detect the presence of a mode command issued to the device. The command may be issued by a station on the earth, and communicated via a telemetry link to the spacecraft. The watchdog circuit may be part of a central processing unit (CPU) with a computer on board the spacecraft, the computer serving to perform various data processing operations for the mission of the spacecraft. The watchdog circuit stores the mode command and then repeats the command during a succession of repetitions.

Abstract: A data processing system executes a plurality of processes in parallel. The processes access shared user records stored in memory serially. One or more data structures are used to track access by processes to the data structures and to the user records. Responsive to a fault occurring in a first parallel process, a signal is given the remaining parallel processes indicating the failure. Responsive to the failure, it is determined if the faulting parallel process had access to one of the data structures. Depending upon the circumstances of access, integrity of the user records may be assumed and the record validated. The data structures themselves can be examined to determine if the contents of memory is reliable. Typically the data structures support use of the memory as a cache.

Abstract: A non-contact type IC card comprising a memory including a manufacturer code area and an error signal output circuit is disclosed. The error signal output circuit outputs an error signal such that an access from a read/write apparatus is allowed when a password coincidence is obtained when a predetermined code is stored in the manufacture code area. On the other hand, when the predetermined code is not stored in the manufacturer code area, the error signal output circuit outputs an error signal such that an access to all the memory area from the read/write apparatus is allowed regardless of a result of the password collation performed by the password collation circuit.

Abstract: A duplicate control and processing unit for telecommunications equipment consisting of two identical control units connected together is described. Each control unit (UC0, UC1) comprises a processing unit (UP0, UP1) which can be active or on standby, a peripheral data random access memory (RAM) for data processed during operation, and several peripheral circuits connected to the rest of the equipment. An EPROM (erasable programmable read-only memory) (CCL0, CCL1) in each processing unit contains the copy selection firmware. The data RAM and the peripheral circuits include a respective double gate access circuit (ACC0, ACC1) which allows selective access to the active processor only. The latter performs the writing cycles synchronously on both the duplicate data RAMs, allowing fast recovery of the operative synchronism by the standby processing unit, after switching due to failure of the active processing unit (FIG. 2).

Abstract: A fault-tolerant bridge/router ("brouter") with a distributed switch-over mechanism of the present invention can tolerate any single failures and does not rely on network reconfiguration (or alternative paths) and, therefore, substantially improves system reliability/availability. The fault-tolerant brouter utilizes a plurality of processing elements communicating through a multiple-bus switching fabric. Each processing element can effectively support two ports, each port providing an interface to an individual LAN. Each LAN is then linked to two different ports on two different processing elements, respectively, thereby providing processing element redundancy. If a processing element fails, bridging/routing functions can be performed by the other, redundant processing element. The functions are switched using the switch-over mechanism. Because the switch-over mechanism is distributed, no centralized control mechanism is required.

Abstract: A method of testing a computer program in a computer system is described. The computer system includes a source code corresponding to the computer program, and a number of tests. The method includes the following steps. A coverage point is inserted into the source code to correspond to a statement in the source code. An executable, corresponding to the source code, is executed using the tests. This generates a result. The result is used to generate a subset of tests that executed the coverage point and tested the statement. Test a second executable using the subset of tests. The second executable corresponds to the source code.

Abstract: All error correction computations for correcting decode errors that corrupt a binary message that is encoded in a two dimensional code, such as a two dimensional self-clocking glyph code, are performed on byte aligned (or, more generally, symbol aligned) symbol sets that span the message but no other variables.

Abstract: In order to effectively avoid faulty or false read error corrections in a digital data processing system, a check is made to see if the number of data read retrials reaches a preset number whose value is less than the maximum number of data read retrials. This checking limits the number of routine runs which can pass through an execution step wherein a check for an uncorrectable error is conducted, to a value which is markedly lower than that of the prior art. Further, if the routine passes once through a flag setting step wherein a flag is set to a preset logic level in the event that an error correcting length exceeds a length of data retrieved from a memory, all checking for uncorrectable errors is by-passed. Hence, the possibility that an uncorrectable error will be erroneously detected an a correctable one is greatly reduced or eliminated.

Abstract: The present invention permits a primary launch engine to display the names of, and information relating to, and cause the execution of diagnostic/test programs and/or batch-type routines for the silicon validation of microprocessors not only in existence at the time the primary launch engine is developed and compiled, but also, diagnostic/test programs and/or batch-type routines for the silicon validation of microprocessors that are developed and/or modified after the primary launch engine is developed and compiled without requiring modifications to, or the recompilation of, the primary launch engine. To do so, the present invention utilizes specialized data files consisting of one or more screen definition files and/or one or more script files wherein each screen definition file contains necessary menu structure and response information for each of the available diagnostic/test programs and wherein each of the script files contains sequencing and parameter information for each of the batch-type routines.

Abstract: The invention provides a fault tolerant output stage for a digital two-conductor bus data communication system of the type having a transmission module and a reception stage which contains a bus signal intermediate processing module and a reception module connected downstream that conditions incoming bus signals for a data processing unit which is connected downstream. A state detection module is connected to the bus lines to detect a short-circuit between the bus lines, in which case the transmission module can be switched over between a difference mode of operation and a single-wire mode of operation under the control of the state detection module.

Abstract: The solution employed by the present invention keeps information about individual exception instances in data structures which are independent of the local storage of the system-level exception management routines. This eliminates confusion and ambiguity because the entire exception handling mechanism can be described and specified in terms of the manipulation of these data structures, independent of the call/return flow of the system-level exception management routines.

Abstract: Defective long filenames (LFNS) are diagnosed and repaired in computer systems that have a file allocation table (FAT) structure (2) and that use both short filenames (SFNs) and long filenames (LFNs). Each LFN comprises at least one LFN entry. Defective LFN entries that are repaired are from the group comprising orphaned LFN entries, malformed LFN entries, improperly terminated chains of LFN entries, and improper matches between LFNs and corresponding SFNs.

Abstract: DASD failures occurring on sector boundaries currently go undetected. While this sort of problem can occur at any time, it usually occurs when the program executing on the computer system's processor is operating on a multisector piece of data and periodically updating that information in auxiliary storage so that the copy in auxiliary storage is relatively up to date with the changes being made by the program. The storage management mechanism of the present invention solves the problem of sector boundary write failures by associating a sequence number with each piece of multisector data. Essentially, the sequence number becomes a property of the particular piece of data itself. When the mechanism retrieves the information from disk, it checks to make sure that all the sequence numbers match. If they do not, a data integrity problem has been detected.

Abstract: The main storage, the communication interface portion and the circuit control module hold transmission data in the buffers until completion of the transmission has been confirmed. When a fault has occurred in the current operating system of the duplexed portions in the configuration elements of the host computer and the multi-circuit control unit, the duplexed portions are changed over from the current operating system to the stand-by system. In this case, information for reproducing data that has been lost due to the change-over is transmitted from the main storage and the circuit control module to the communication interface portion which has become the new current operating system. The communication interface portion which has become the new current operating system restarts the processing based on this information.

Abstract: A method and apparatus for initializing both processors in a master/checker fault detecting microprocessor. A microcode initialization routine is run by each processor upon reset of both of the processors in the pair. The routines cause each processor to be initialized, such that the two processors complete initialization at the same time and operate in a lock-step manner.

Abstract: A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits - gate arrays - it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data.