Abstract: A memory management system for maximizing the number of contiguous free buffers to reduce the required number of free buffer pointers. Accordingly, with this invention a buffer memory is divided into two disjoint areas with one area having only contiguous free buffers while the other area has a combination of free and used buffers. This invention also has a means for maximizing the number of contiguous free buffers by using the buffers in the area having only contiguous free buffers only if there are no free buffers in the other area having both used and free buffers.

Abstract: A system and method for maintaining data coherency in a system in which data is replicated on two or more servers. Each server is able to update the data replica present on the server. Updates are logged for each server. Reconciliation of server data replicas is aggressively initiated upon the occurrence of predefined events. These events include arrival at a scheduled time, a request for data by a client system, server and network failure recovery. Reconciliation is managed by a coordinator server selected to ensure that at most one coordinator server per network partition is selected. Logged updates are merged and transmitted to each server containing a data replica. The logged updates are applied unless a conflict is detected. Conflicts are collected and distributed for resolution. Reconciliation is managed between servers without regard to operating system or physical file system type.

Abstract: A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

Abstract: In a superscalar processor capable of executing two integer instructions in parallel, an array of comparators is provided to check for all combinations of register dependency between a pair of sequential program instructions. Additional logic is provided to validate the register fields of the instructions. If no impermissible dependencies are detected and all register fields are valid, the instructions are issued and executed in parallel. Otherwise, the instructions are executed sequentially.

Abstract: An apparatus receives a query from a process controller containing a process variable address representing a storage location for a process variable in a network of field devices. A communication standard type and an unique field device address is associated with each field device. An associating section identifies a field device address and a communication standard type associated with each of a plurality of process variable addresses. An extracting section matches the stored process variable address with a process variable address in the associating section and extracts the associated field device address and the associated communication standard type from the associating section. A generating section generates a field device request containing the extracted associated field device address as a function of the extracted associated communication standard type. The field device request is conveyable over a communication line to address the storage location represented by the stored process variable address.

Abstract: An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic instruction pairs is developed. The algorithm is then applied to three interlock collapsing ALU means implementations that have been proposed. The critical path for calculating the carries is first presented. Next the expression for generating these carries is used to derive a fast implementation for generating overflow which is implemented in the apparatus.