Abstract: A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.

Abstract: An FBGA packaged device including a die adhered to a substrate with a small gap being formed between the die and substrate. An opening is formed through the substrate adjacent the center portion of the die. An encapsulating mold is formed around the die extending into the gap and also filling the channel. At least one barrier is disposed in the gap between the substrate and the die adjacent the channel to control the flow path of the encapsulating material as the mold is formed in the package.

Abstract: A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead being divided into an inner portion and an outer connecting portion. A first tape adhering under the inner portions of the leads fastens the first chip and the first bonding wires electrically connect the first chip with the inner portions. A second tape adhering upon the inner portions of the leads fastens the second chip and the second bonding wires electrically connect the second chip with the inner portions. The second tape has a thickness so as to avoid the first bonding wires touching the second chip. The multi-chip package enables to package at least two chips by a LOC lead frame without turnover action during wire-bonding.

Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.

Abstract: A semiconductor device has multiple, stacked dies in which the back surfaces of each die can be biased to the same or a different electrical potential. The device includes a substrate having a plurality of electrically conductive leads arrayed around an electrically conductive die-mounting pad. A first semiconductor die is mounted on and in electrical connection with the pad. A uniformly thin spacer is mounted on the first die inside the inner periphery of the wire bonding pads thereon and such that the spacer is electrically isolated from the first die. A second die is mounted on the spacer with a layer of electrically conductive material. The layer of conductive material and the die pad are electrically connected to the same or different leads of the substrate such that, by connecting the leads to the same or different electrical potentials, the respective back surfaces of the dies are biased to the same or different potentials.

Abstract: An assembly of semiconductor devices, wherein the device comprises a chip with electrodes on one side for electrical connection with an external circuit, and a flexible base comprising an insulation film having an inner opening and outer openings outside the inner opening, and the conductor pattern comprising a plurality of inner leads having an end extending to the inner opening of the film, and the outer leads being positioned to bridge the outer opening of the film; and the chip being mounted on the flexible base by bonding the lead-out electrodes thereof to the ends of inner leads, and wherein the devices are assembled to be connected with each other through the outer leads of semiconductor devices which are adjacent to each other, and the semiconductor chips, which face a substrate on which the assembly is to be mounted, have external connection electrodes, on which an external connection terminal for mounting is provided.