Patents Examined by Patrick Borges
  • Patent number: 10037157
    Abstract: Techniques are provided for implementing a zero detection feature in the middle of a I/O driver stack that is able to function properly on migration of a thickly-provisioned logical disk to a thinly-provisioned logical disk. This may be accomplished by creating the destination thinly-provisioned logical disk with a Zero Detect mode that is initially set to active upon a migration. The zero detection feature implemented in the middle of the I/O driver stack is configured to require any writes to a logical disk to be buffered when that logical disk is in active Zero Detect mode, and to automatically apply zero detection to such writes to prevent writing entire blocks of zeroes. The Zero Detect mode may then be set to passive upon completion of the migration, allowing zero detection to be applied only to select write operations in the normal course of operation.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 31, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Milind M. Koli, Timothy C. Ng
  • Patent number: 9940128
    Abstract: A method can include receiving a first memory load request by a conditional load with time out (CLT) device at a first time. The first memory load request can specify a first condition. A first determination of whether the first condition is satisfied is performed. The CLT device determines a wait period when the first condition is not satisfied. A reply is issued. The reply indicates that the first condition is satisfied when the first condition is satisfied. The reply indicates that the first condition is not satisfied when the duration of the wait period exceeds a time-out threshold. When the first condition is not satisfied, a first memory store request can be received during the wait period and a second determination of whether the first condition satisfied performed. The reply indicates that the first condition is satisfied when the second determination is that the first condition is satisfied.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 9933947
    Abstract: Techniques are described for processing multi-page write operations to maintain write level consistency. A multi-page write spanning multiple cache pages is directed to a target device and received on a first data storage system where writes to the target device are synchronously replicated to a second data storage system. On the first data storage system, each of the multiple cache pages may be synchronously replicated to the second data storage system. A lock on each of the cache pages is not released until an acknowledgement is received regarding successful replication of the cache page. On the second data storage system, requests to replicate the multiple cache pages containing write data of the multi-page write are received and processed using locks of corresponding cache pages on the second data storage system. Such techniques also handle concurrent reads and/or writes. Deadlock detection and resolution processing may be performed for concurrent writes.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Deepak Vokaliga, Benjamin Yoder, Vadim Longinov, George Quill, Benoit Joseph Merlet
  • Patent number: 9928174
    Abstract: A consistent caching service for managing data consistency between a cache system and backing store is provided. The consistent caching service compares an origin token and a parity token associated with the cached copy of the data item to determine consistency of the data item. The origin and parity tokens may be generated by an operation that caused population of the data item to the cache. The parity token may be invalidated by a write operation of the data item, thus causing a mismatch between the two tokens.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 27, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Paul Connell
  • Patent number: 9916105
    Abstract: Providing for a memory apparatus configured for improved data management for a two-terminal memory array is described herein. By way of example, disclosed embodiments relate to page management and transfer of data between page-sized subsets of a page buffer, and respective pages within one or more memory banks of the two-terminal memory array. The memory apparatus can emulate a larger page size than a physical page buffer utilized by the memory apparatus, to provide compatibility with different page size defaults while lowering current consumption by the page buffer. This can facilitate large or small array operations, taking advantage of higher efficiencies of two-terminal memory devices. In addition, page buffer data management can facilitate interleaved data transfers among multiple banks of memory, facilitating large memory capacities for a disclosed memory apparatus.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: March 13, 2018
    Assignee: CROSSBAR, INC.
    Inventor: Mehdi Asnaashari