Patents Examined by Patrick Cullen
  • Patent number: 12610756
    Abstract: A manufacturing method of a nitride semiconductor device includes: introducing a p type impurity into at least a part of an upper layer portion of a first nitride semiconductor layer to form a p type impurity introduction region; forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer so as to include the p type impurity introduction region; and performing an anneal treatment in a state where the second nitride semiconductor layer is formed on the first nitride semiconductor layer.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 21, 2026
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Takashi Okawa, Kenta Watanabe
  • Patent number: 12599019
    Abstract: An embedded packaging structure and a manufacturing method thereof are disclosed. The method includes: providing a bearing plate with a first metal seed layer; processing on the first metal seed layer to obtain a substrate; removing the bearing plate to obtain the substrate, and processing on the substrate to obtain a first and a second cavities penetrating therethrough; assembling a first component in the first cavity, assembling a connecting flexible board in the second cavity, processing on a second side of the substrate to obtain a second insulating layer; processing on a first side of the substrate to obtain a second circuit layer, assembling a second component on the second circuit layer; bending the substrate through the connecting flexible board to form an included angle less than 180 degrees on the first side, and packaging the first side by using a packaging material to obtain a packaging layer.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: April 7, 2026
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd.
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Gao Huang
  • Patent number: 12526884
    Abstract: A method for manufacturing a light-emitting device includes forming the quantum dot layer, wherein the forming the quantum dot layer includes performing first application of applying, on a position overlapping with the substrate, a first solution including quantum dots, a ligand, a first inorganic precursor, and a first solvent, the quantum dots each including a core and a first shell coating the core, the ligand coordinating with each of the quantum dots, performing temperature raising of raising a temperature until the ligand melts and the first solvent vaporizes after the performing first application, performing first temperature lowering of lowering a temperature to a melting point of the ligand or lower after the performing temperature raising, and performing first light irradiation of epitaxially growing the first inorganic precursor around the first shell by first light irradiation after the performing first temperature lowering to form a second shell coating the first shell.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 13, 2026
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masumi Kubo
  • Patent number: 12489032
    Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: December 2, 2025
    Assignee: Intel Corporation
    Inventors: Feras Eid, Aleksandar Aleksov, Henning Braunisch, Adel Elsherbini, Thomas L. Sounart, Johanna Swan
  • Patent number: 12453219
    Abstract: A light-emitting diode includes an epitaxial unit, a first electrode, and a second electrode. One of the first electrode and the second electrode includes a first reflective layer, a wire-bonding electrode layer, a second reflective layer wrapping a portion of the wire-bonding electrode layer, and a stress adjustment layer which wraps around the first reflective layer. The first reflective layer includes platinum, and the second reflective layer includes a material which has a Mohs hardness of not less than 6. The stress adjustment layer has a Mohs hardness of not less than 6, and the stress adjustment layer has a thickness that is 65% to 75% of a thickness of the first reflective layer.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: October 21, 2025
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Bo-Yu Chen, Yu-Tsai Teng, Chung-Ying Chang
  • Patent number: 12412801
    Abstract: Packaged semiconductor device having a heat sink, wherein the heat sink has a top, a bottom, lateral surfaces that connect the top to the bottom, and, extending within the heat sink, a cooling structure with an inlet line as well as an outlet line for a cooling medium, and is composed of an electrically conductive material with a first coefficient of thermal expansion at the top and with a second coefficient of thermal expansion at the bottom, a die is arranged on each of the top and the bottom of the heat sink and is connected to the heat sink in an electrically conductive manner, the coefficients of thermal expansion of the top and of the bottom of the heat sink correspond in each case to the coefficient of thermal expansion of the die arranged thereon or differ from the coefficient of thermal expansion of the die arranged thereon by at most 10% or by at most 20%.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: September 9, 2025
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Jens Kowalsky
  • Patent number: 12389661
    Abstract: A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: August 12, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chen Lee, Ren-Kai Chen, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 12341113
    Abstract: A semiconductor structure includes two circuit regions and two inner seal rings, each of which surrounds one of the circuit regions. Each inner seal ring has a substantially rectangular periphery with four interior corner stress relief (CSR) structures. The semiconductor structure further includes an outer seal ring surrounding the two inner seal rings. The outer seal ring has a substantially rectangular periphery without CSR structures at four interior corners of the outer seal ring. The outer seal ring includes a plurality of first fin structures located between each of the two inner seal rings and a respective short side of the outer seal ring. Each first fin structure is parallel with the respective short side of the outer seal ring. Lengths of the first fin structures gradually decrease along a direction from the inner seal rings to the respective short side of the outer seal ring.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: June 24, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shan-Yu Huang, Hsueh-Heng Lin, Shih-Chang Chen, Hsiao-Wen Chung, Yilun Chen