Abstract: A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction.

Abstract: An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables.

Abstract: Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.

Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.

Abstract: A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.

Abstract: A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes of a predetermined size, based on an area density of the each small region, calculating a second dimension correction amount in accordance with a line width dimension of the pattern to be written in the each small region, correcting the first dimension correction amount by using the second dimension correction amount, and resizing the line width dimension of the pattern by using a corrected first dimension correction amount, and outputting a result of the resizing.

Abstract: A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.

Abstract: An electro-migration verifying method is comprised of: a data inputting process step; a netlist updating process step (first process operation) for updating a netlist which is constructed by a wiring line parasitic element and a device element based upon a current density limit value database, a characteristic variation database, and wiring line current information; a current density calculating process step (second process operation) for calculating current density of the wiring line parasitic element from a device current and the updated netlist; a wiring line current information updating process step (third process operation) for updating the wiring line current information based upon the current density; a current density limit value comparing/judging process step (fourth process operation) for judging whether or not a current density value is located within the current density limit value based upon the updated wiring line current information and the current density limit value database; an electro-migra

Abstract: A method for identifying specification window violations for a system is described. The method includes generating a sample set of input parameters. The system is simulated using the sample set to generate an output set. A mathematical model is best-fit to the output set. A set of desirability functions is defined to an out-of-spec condition. The model is then searched using the desirability functions to identify a worst-case data point. The worst-case data point can then be determined as either being within specification or out of specification.

Abstract: A method for placing a system on a structured application specific integrated circuit (ASIC) using an electronic design automation tool is disclosed. A subregion that includes an illegal position in a placement solution is identified. All structured ASIC cells in the subregion are removed. Positions for all the structured ASIC cells that are legal are determined.

Abstract: A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks.

Abstract: A hardware verification programming description generation apparatus includes: a behavior synthesis section, for a circuit of hardware that operates in accordance with a multi-phase clock, for dividing the hardware into blocks corresponding to clock systems and performing a behavior synthesis on each of the divided blocks, based on a behavioral description, the behavioral description only describing a process behavior of the hardware but does not describe information regarding a structure of the hardware; and a clock precision model generation section for generating clock precision models using the behavior-synthesized data, the clock precision model capable of verifying the hardware at a cycle precision level.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern.

Abstract: Systems and methods are disclosed herein which compensate for the loss in design information that occurs when the design is represented in traditional functional descriptions. An automated multiple voltage/power state design process includes creating a plurality of design objects; processing a design definition according to the voltage effects design object; and generating a modified design output such that communication between a plurality of design process steps, wherein the plurality of design process steps include a parsing step, a RTL simulation step, a synthesis step, a gate simulation step, formal verification step, and physical design and verification step in accordance with the voltage effects design object.

Abstract: A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

Abstract: Methods of implementing circuits while automatically taking multi-cycle paths into account. A processor-implemented method can include inputting a behavioral description of the circuit, a simulation test bench for the circuit, and a library that includes at least one synchronous element. The synchronous element includes code that, when simulated, outputs tracking information including a minimum number of clock cycles between state changes for terminals of the synchronous element. The behavioral description is synthesized to generate a netlist description of the circuit. The netlist description includes at least one instance of the synchronous element. The netlist description is simulated using the simulation test bench and the library. The simulation outputs a description of all multi-cycle paths in the netlist description based on the tracking information output by all instances of the synchronous element in the netlist description.

Abstract: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

Abstract: An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, a postcondition, and an invariant condition for the use case. The operation extracting unit selects an event flow of an unprocessed path from the specification data and extracts an unprocessed operation (description) from the event flow selected. The second setting unit sets a precondition and a postcondition for the operation based on the extracted operation (description). The determining unit determines whether the invariant condition is valid.