Abstract: The surface acoustic wave device has the surface acoustic wave transducer, which consists of the positive electrode finger 102, the negative electrode finger 204, and the floating electrode 300, which are formed on the surface of the langasite single crystal substrate, where the substrate orientation and the surface acoustic wave propagation direction are chosen so that it may have the natural unidirectional property. When the wavelength of the surface acoustic wave is ?, each above-mentioned electrode is formed along the surface acoustic wave propagation direction, so that the width of above-mentioned positive electrode finger and the negative electrode finger may be about ?/8, the distance g between each center of the positive electrode finger and the floating electrode may be 13/40??g?14/40?, and the width W of the floating electrode may be 11/40??W?13/40?.

Abstract: A S/N enhancer using the magnetostatic wave signal. The S/N enhancer comprises a balun coupler for dividing an input signal into a first and second signals having the same power, the second signal having the phase difference of 180 degree with respect to the first signal; a saturation magnetostatic wave filter for receiving the first signal output from the balun coupler, converting that into a magnetostatic wave signal, and oppositely converting the magnetostatic wave signal, wherein the power of the magnetostatic wave signal is saturated if the first signal has the power of equal to and more than that of a noise signal; a delay line having the linearity to transmit the second signal output from the balun coupler; and a power synthesizer for synthesizing the respective signals output from the saturation magnetostatic wave filter and the delay line.

Abstract: The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second active regions extending into a second semiconductive material. At least one of the first and second semiconductive materials can comprise crystalline Si/Ge. The logic construction can comprise NOR circuitry and/or NAND circuitry, as well as higher level logic cells, such as latches. Further, the logic circuit construction can be associated with a semiconductor-on-insulator structure, and on versatile substrates. The invention includes three-dimensional logic cell layout configurations for enhanced wireability and logic cell density, which can lead to enhanced performance.

Abstract: A piezoelectric resonator includes a substrate, a vibration unit disposed on the substrate and having a structure in which at least one pair of an upper electrode and a lower electrode opposed to each other, the upper and lower electrodes sandwiching the upper and lower surfaces of an internal thin-film portion including at least one layer of a piezoelectric thin-film, and an external thin-film portion provided under the lower electrode and including at least one layer of a piezoelectric thin-film or a dielectric thin-film, the vibration unit being vibrated in an n-th harmonic (n is an integer of 2 or more), the upper electrode and the lower electrode being provided substantially in the positions of the loops of the n-th harmonic.

Abstract: A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with the existing software.

Abstract: An improved circuit for splitting or for joining radio-frequency powers, having a main line (7) which is connected between an input port (1) and a first output port (3), and having a branch line (11) which branches off from the main line at a branching point (9) and leads to a second output port (5), is distinguished in that a compensating element (61) is provided which, in particular, is adjustable or can be fitted and removed differently, and which can be varied, varying the capacitance of at least one capacitor (C1, C2, C3) which is connected in the branch line (11), and/or varying the electrical length of a spur line (37) which is coupled to the branch line (11), such that the change in the magnitude of the power which is tapped off also makes it possible to compensate at the same time for the resistance change which is caused by the change in the power split.

Abstract: Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT1, OUT2 therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT 1 and OUT 2 are combined in-phase.

Abstract: A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.