Abstract: A cache memory serves for accelerating accesses to an external memory of a microprocessor. Instead of an actually occurring hit event, a cache miss is signaled to the microprocessor. The reversal is randomly controlled. This disguises the current profile of cache hit and miss events, which enhances the security against statistical attack techniques based on the evaluation of the current profile.

Abstract: A system and corresponding method for improving set-top box boots up efficiency while, at the same time, reducing the memory allocation required for set-top box boot-up is disclosed. The boot-up method includes performing a vertical direct memory access transfer of relevant program instructions from a system non-volatile memory to system main memory. The transferred program instructions are then re-arranged into consecutive locations within the main memory.

Abstract: A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.

Abstract: The invention concerns a method (200) and system (100) for searching for duplicate data. The method (200) includes the steps of: generating (212) at least one identifier from at least one portion of a first segment of data using a unique identifier function; generating (216) at least one identifier from at least one portion of a second segment of data using the unique identifier function; and comparing (220) at least one identifier associated with the first segment of data with at least one identifier associated with the second segment of data to determine whether the first segment of data is substantially identical to the second segment of data.

Abstract: A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

Abstract: A system and method are provided for efficiently prefetching data in a pointer linked data structure (140). In one embodiment, a data processing system (100) is provided including a processor (110) capable of executing a program, a main-memory (115) and a prefetch engine (175) configured to prefetch data from a plurality of locations in main-memory in response to a prefetch request from the processor. When the data in main-memory (115) has a linked-data-structure having a number nodes (145) each with data (150) stored therein, prefetch engine (175) is configured to traverse the linked-data-structure and prefetch data from the nodes. The prefetch engine (175) is configured to determine from data contained in a prefetched first node (145A) and an offset value a new starting address for a second node (145B) to be prefetched.

Abstract: An operation method for controlling memorized page access attribute of the memory and its structure, particularly a control method for a low-level driver or system chipset to perform the control of read and write to partial areas of the memory, mainly by means of making use of buffer memory to configure procedures to perform operation area configuration of memory, and by means of practical operation procedures to confirm the operation mode of the said area, to further control said region in such modes as read only, write only, write once, read once, etc., to prevent programs which have been loaded into the memory and will be executed and passwords which have been verified from being intruded by illegal hacker, virus, etc, to provide a common protective design to the system safety.

Abstract: A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.

Abstract: The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.

Abstract: A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of receive ports receiving the data packets and a queue of addresses of a plurality of storage areas in the memory available for storing the received data packets. The address generator generates memory addresses to store the received data packets in the plurality of storage areas of the memory and includes first and second registers. The first register receives an address from the queue of addresses and provides a first part of the memory address, and the second register counts write cycles to the memory and provides the count result as a second part of the memory address.

Abstract: An information processing apparatus and method and a program storage medium by which a recording medium of an apparatus connected to a network to which the information processing apparatus is connected can be utilized effectively wherein if reservation of recording of a predetermined program is performed for a video recorder, then a data amount necessary to record the reserved program is calculated. Then, those of apparatus connected to a network which include a recording medium which can record the calculated data amount are searched for. In response to a result of the search, a distribution of data amounts to be recorded into the recording media of those apparatus is determined. Then, areas are secured in the recordable areas of the recording media so that the determined data amount may be recorded.

Abstract: A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration.

Abstract: A computer system includes a processing unit, a system memory, and a memory controller coupled to the processing unit and the system memory. According to the present invention, the memory controller accesses the system memory to obtain prefetch data and transmits the prefetch data to the processing unit in a prefetch write operation specifying the processing unit in a destination field. In one embodiment, the memory controller transmits the prefetch write operation in response to receipt of a prefetch hint from the processing unit, which may accompany a read-type request by the processing unit. This prefetch methodology may advantageously be implemented imprecisely, with the memory controller responding to the prefetch hint only if a prefetch queue is available and ignoring the prefetch hint otherwise. The processing unit may similarly ignore the prefetch write operation if no snoop queue is available.

Abstract: A non-uniform memory access (NUMA) computer system and associated method of operation are disclosed. The NUMA computer system includes at least a remote node and a home node coupled to an interconnect. The remote node contains at least one processing unit coupled to a remote system memory, and the home node contains at least a home system memory. To reduce access latency for data from other nodes, a portion of the remote system memory is allocated as a remote memory cache containing data corresponding to data resident in the home system memory. In one embodiment, access bandwidth to the remote memory cache is increased by distributing the remote memory cache across multiple system memories in the remote node.

Abstract: A method and software for managing memory are provided in which objects residing in session memory are formatted so the references contained in the objects are in a machine-independent format, namely, that the references are encoded numerically. An exit table is provided to handle references with session memory that refer to locations in call memory, in which each entry in the exit table is associated with a corresponding reference in session memory and contains a pointer to the location in call memory.

Abstract: A flash memory controller with a volatile program and data memory is disclosed. The controller loads microcode and data into the program and data memory from a flash memory array upon powerup of the controller. If an error occurs during the download or the microcode does not exist in the flash memory array, then the controller loads microcode and data into the program and data memory from the host computer. In some embodiments of the invention, an initial code is downloaded to the controller so that an evaluation of the configuration of the controller and the flash memory can be communicated to a host computer. The host computer then downloads for storage into the flash memory a tailored microcode and restarts the controller so that the tailored microcode is loaded from the flash memory and executed. In some embodiments, a protection circuit is provided to protect the microcode from accidentally being erased from the flash memory.

Abstract: A non-uniform memory access (NUMA) computer system includes a first node and a second node coupled by a node interconnect. The second node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, and a controller coupled to the local interconnect. In response to snooping an operation from the first node issued on the local interconnect by the node controller, the controller signals acceptance of responsibility for coherency management activities related to the operation in the second node, performs coherency management activities in the second node required by the operation, and thereafter provides notification of performance of the coherency management activities.

Abstract: A flash memory block erase operation permits multiple blocks to be erased simultaneously, even if the blocks are non-contiguous. A command sequence outputs multiple block addresses to the flash memory controller, which stores indicators of those addresses. When the command is completed, the flash memory initiates a block erase on all the specified blocks. The special command can be a multi-cycle bus command, made up of a sequence of single-cycle bus transfers using a standard format for the bus. The flash memory interface can contain the capability to interpret the command, retain the information transferred during the multiple bus cycles, and initiate the block erase operation after all the block addresses for that command have been received.

Abstract: A data processing device contains a time division multiplexed multiport memory. The timing of memory access is defined in time-slots for access to the memory from respective ports. Timing is generated asynchronously with a handshake in response to a ready signal indicating completion of access during a previous time-slot.

Abstract: A data buffer memory management method and system is provided for increasing the effectiveness and efficiency of buffer replacement selection. Hierarchical Victim Selection (HVS) identifies hot buffer pages, warm buffer pages and cold buffer pages through weights, reference counts, reassignment of levels and ageing of levels, and then explicitly avoids victimizing hot pages while favoring cold pages in the hierarchy. Unlike LRU, pages in the system are identified by both a static manner (through weights) and in a dynamic manner (through reference counts, reassignment of levels and ageing of levels). HVS provides higher concurrency by allowing pages to be victimized from different levels simultaneously. Unlike other approaches, Hierarchical Victim Selection provides the infrastructure for page cleaners to ensure that the next candidate victims will be clean pages by segregating dirty pages in hierarchical levels having multiple separate lists so that the dirty pages may be cleaned asynchronously.