Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.

Abstract: There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor.

Abstract: According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground.

Abstract: There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor.

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition.

Abstract: [PROBLEMS] To easily associate the parameters representing the acoustic characteristic of a hearing aid with the audibility of the hearing aid user, shorten the time for adjusting the hearing aid, and improve the accuracy of the adjustment of the parameter. [MEANS FOR SOLVING PROBLEMS] By applying a two-dimensional matrix for changing the acoustic parameters of the hearing aid, a person adjusting the hearing aid can easily change the acoustic parameters depending on the audibility of the hearing aid user, the accuracy of the adjustment of the acoustic parameters is improved, and the period of time for adjusting the hearing aid is shortened.

Abstract: Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Abstract: A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing be overcome to provide reduced critical dimension elements.

Abstract: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Abstract: A semiconductor device and methods of manufacturing and operating the semiconductor device may be disclosed. The semiconductor device may comprise different nanostructures. The semiconductor device may have a first element formed of nanowires and a second element formed of nanoparticles. The nanowires may be ambipolar carbon nanotubes (CNTs). The first element may be a channel layer. The second element may be a charge trap layer. In this regard, the semiconductor device may be a transistor or a memory device.

Abstract: A non-volatile memory device on a substrate layer (2) comprises source and drain regions (3) and a channel region (4). The source and drain regions (3) and the channel region (4) are arranged in a semiconductor layer (20) on the substrate layer (2). The channel region (4) is fin-shaped and extends longitudinally (X) between the source region and the drain region (3). The channel region (4) comprises two fin portions (4a, 4b) and an intra-fin space (10), the fin portions (4a, 4b) extending in the longitudinal direction (X) and being spaced apart, and the intra-fin space (10) being located in between the fin portions (4a, 4b), and a charge storage area (11, 12; 15, 12) is located in the intra-fin space (10) between the fin portions (4a, 4b).

Abstract: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.

Abstract: A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer.

Abstract: In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween.

Abstract: A package substrate of the present invention at least comprises a metal substrate and a plurality of light emitting dies. The metal substrate is provided thereon with at least one trench. The trench is recessed into the surface of the metal substrate through an insulating layer. The light emitting dies are secured in the trench and electrically connected to a predetermined wiring layer on the metal substrate by metal wires, thereby obtaining a light emitting die package substrate with good thermal conductivity, high heat dissipation, separate electrical and thermal paths and a simple and firm structure.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate.

Abstract: A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure.

Abstract: A semiconductor device includes a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.

Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; device regions formed on the semiconductor substrate, the device regions having a length direction in a predetermined direction; a plurality of transistors having gate electrodes, respectively, the gate electrodes extending in a direction approximately perpendicular to the predetermined direction, the plurality of transistors having a source/drain region and a channel region having a channel direction approximately parallel to the predetermined direction in the device region; a plurality of SRAM cells disposed in an array, each of the plurality of SRAM cells including the plurality of transistors; and a dummy region made of the substantially same material as that of the device regions, the dummy region being formed between the outermost device regions of the SRAM cells adjacent to each other in the direction approximately perpendicular to the predetermined direction, the dummy region having a length directi