Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

Abstract: A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator circuit are referred to ground to reduce the total DC current draw, e.g., by a factor of 7. The multiple use of the input stage bias and grounded connections to the positive and/or negative inputs reduce the overall current requirements of the differential comparator circuit substantially while maintaining full operating speed as compared to conventional differential comparator circuits. In one embodiment using the low power differential comparator circuit, a clock receiver implements hysteresis which is relatively independent from variations in environmental factors such as temperature, and from power supply variations. In this embodiment, the input stage of a low power comparator circuit is biased by the output of a bias circuit.