Patents Examined by Paul E Block, II
  • Patent number: 6329260
    Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: December 11, 2001
    Assignee: Intersil Americas Inc.
    Inventors: Glenn Alan DeJong, Akira Ito, Choong-Sun Rhee, Jeffrey Johnston, Michael D. Church, Kantilal Bacrania