Abstract: The present invention is a semiconductor device having a capacitor employing ferroelectrics as a capacitor insulating film. The semiconductor device comprises a semiconductor substrate 11, an insulating film 12 formed on the semiconductor substrate 11, and a capacitor including (a) a lower electrode formed on the insulating film and made of a refractory metal whose face orientation (111) appears on an upper surface thereof, (b) a capacitor insulating film formed on the lower electrode and made of at least two layers consisting of a ferroelectrics film including Pb having a face orientation (111) and a ferroelectrics film including Pb having a face orientation (100), and (c) an upper electrode 15 formed on the capacitor insulating film 14.

Abstract: The present invention comprises a method for preventing particle formation in a substrate overlying a DARC coating. The method comprising providing a semiconductor construct. A DARC coating is deposited on the construct with a plasma that comprises a silcon-based compound and N2O. The DARC coating is exposed to an atmosphere that effectively prevents a formation of defects in the substrate layer. The exposed DARC coating is overlayed with the substrate.

Abstract: In the fabrication of capacitors, a TiO2 film is formed from a TiN film by means of heat-treatment within an atmosphere which does not contain oxygen. This serves to prevent the polysilicon which forms the bottom electrode from being oxidized during heat-treatment. Thus, once the bottom electrode has been formed on the silicon wafer, a TiN film and RuO2 film are formed, and the silicon wafer is heat-treated in an atmosphere which does not contain oxygen. In this manner, a dielectric film that is a TiO2 film and a top electrode that is a ruthenium film are obtained.

Abstract: A low dielectric constant material, suitable for use as an interlayer dielectric in microelectronic structures includes a porous silicon oxide layer. In a further aspect of the present invention, a porous oxide of silicon is formed by the room temperature oxidation of porous silicon. The room temperature oxidation is achieved by exposing a porous silicon layer to a solution of hydrochloric acid, hydrogen peroxide, and water, in the presence of a metal catalyst.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: Disclosed is a method for making an air bridge in an electronic device. This method uses amorphous silicon carbide to protect electrical conductors in the device during formation of the bridge. The silicon carbide also provides hermetic and physical protection to the device after formation.

Abstract: Phase Change Material (“PCM”) are used to reduce the range of temperature excursions in a semiconductor die attached to an interconnect substrate in the flip chip technology. In one embodiment a PCM underfill, which comprises PCM microspheres interspersed within a polymer, is dispensed in the interface area between the semiconductor die and the interconnect substrate. Reduction of the range of temperature excursions in the semiconductor die is achieved since the PCM underfill acts as a cushion to dampen the range of temperature excursions of the semiconductor die. During dissipation of power pulses in the semiconductor die, the PCM underfill absorbs energy from the semiconductor die by changing phase from solid to liquid without a concomitant rise in the temperature of the PCM underfill. Thus, the energy released when power pulses are being dissipated in the semiconductor die does not result in a rise in the temperature of the PCM underfill.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Abstract: The semiconductor device includes and the method for fabricating the same forms a damaged region under a gate electrode to improve device performance and simplify the process. The semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in first predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed over a second predetermined area of the substrate; sidewall spacers formed on both sides of the gate electrode; source and drain regions at both sides of the gate electrode; and the damaged region at boundary of the buried insulating layer under the gate electrode.