Abstract: A storage assembly includes a plurality of multi-unit storage device is provided with a failover procedure that does not require hot-swap capability. Individual units are aggregated into a storage array by an aggregation procedure such as RAID. When a failure occurs data from the failed unit is transferred to a hot spare unit. Also, data from other units is transferred by simulating failure of those units and then the complete device can be removed. In small storage networks all the units may be aggregated as a single array and a spare auxiliary device is summoned and integrated into the array prior to the simulated failure. In larger systems there may be two layers of aggregation and failover is run by the second level of aggregation.
Type:
Grant
Filed:
April 24, 2002
Date of Patent:
July 5, 2005
Assignee:
3Com Corporation
Inventors:
Ciaran Murphy, Richard A Gahan, John Healy
Abstract: A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.