Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.

Abstract: A method for managing storage allocation includes adaptively determining, by a storage device processor, a region width across disk spaces for a group of storage devices that is inversely proportional to a number of nodes sharing a particular storage device. An adaptive storage device allocation region of the particular storage device is created based on the determined region width across the disk spaces for the group of storage devices.

Abstract: A data storage device includes a memory that has a three-dimensional (3D) memory configuration, a controller, and a plurality of memory ports. The controller is configured to read mapping data from the memory. The mapping data maps the plurality of memory ports to the plurality of storage elements. The controller is further configured to, in response to receiving a command associated with a logical address, determine a physical address of the memory corresponding to the logical address, the physical address corresponding to a group of storage elements of the plurality of storage elements. The controller is further configured to select a memory port of the plurality of memory ports, where the memory port is mapped to the group of storage elements. The controller is further configured to access the group of storage elements via the memory port to perform first command.

Abstract: A data storage system can scan one or more information stores of primary storage and analyze the metadata of files stored in the one or more information stores of primary storage to identify multiple, possibly relevant, secondary copy operations that can be performed on the files. The storage system can also identify primary storage usage information of each file during the scan and use that information to generate reports regarding the usage of the primary storage.

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract: One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty.

Abstract: An information processing apparatus includes a processor, a first memory, and a second memory, wherein the second memory includes a first data storage region having a first data capacity and a second data storage region having a second data capacity smaller than the first data capacity, and the processor is configured to, in a case of executing first processing, select the first data storage region as a storage region for data to be written into the second memory by the first processing, and select the second data storage region as a storage region for data to be written into the second memory by second processing, and in a case of not executing the first processing, select the first data storage region as a storage region for data to be written from the first memory to the second memory by the second processing.

Abstract: A method of operating a memory system includes; storing data in a buffer region of the nonvolatile memory, later issuing a migration request directed to the data stored in the buffer region and executing a migration operation to move the data from buffer region to a main region of the nonvolatile memory device. Upon completion of the migration operation, marking a migration operation completion time, and after an initial verify shift (IVS) time has elapsed following the migration operation completion time, updating a mapping table associated with the data in view of the executed migration operation.

Abstract: An integrated-circuit device (1) comprises a processor (7), memory (13) for storing executable code, and memory protection logic (9). The memory protection logic (9) is configured to: determine the state of a read protection flag for a protected region of the memory (13); detect a memory read request by the processor (7); determine whether the read request is for an address in the protected region of the memory (13); determine whether the processor (7) issued the read request while executing code stored in the protected region of the memory (13); and deny read requests for addresses in the protected region if the read protection flag for the protected region is set, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor (7) issued the read requests while executing code stored in the protected region.

Abstract: Embodiments of the invention relate to storage allocation in a storage system. One embodiment includes adaptively determining, by a storage device processor, a region height across disk spaces of a group of storage devices that is proportional to a number of connected storage devices. The storage device processor adaptively determines a region width across the disk spaces for the group of storage devices that is inversely proportional to a number of nodes sharing a particular storage device.

Abstract: Memory pages that are allocated to a memory consumer and continue to be accessed by the memory consumer are included in a free list, so that they may be immediately allocated to another memory consumer as needed during the course of normal operation without preserving the original contents of the memory page. When a memory page in the free list is accessed to perform a read, a generation number associated with the memory page is compared with a stored copy. If the two match, the read is performed on the memory page. If the two do not match, the read is not performed on the memory page.

Abstract: A method of operating a memory system includes; storing data in a buffer region of the nonvolatile memory, later issuing a migration request directed to the data stored in the buffer region and executing a migration operation to move the data from buffer region to a main region of the nonvolatile memory device. Upon completion of the migration operation, marking a migration operation completion time, and after an initial verify shift (IVS) time has elapsed following the migration operation completion time, updating a mapping table associated with the data in view of the executed migration operation.

Abstract: A system, method, and computer program product are provided for managing miss requests. In use, a miss request is received at a unified miss handler from one of a plurality of distributed local caches. Additionally, the miss request is managed, utilizing the unified miss handler.

Abstract: A method of caching data is performed by a respective computer having one or more processors storing one or more storage management programs for execution by the one or more processors, non-volatile secondary storage and non-volatile cache memory. The method includes receiving from the non-volatile cache memory information identifying an amount of available storage in the non-volatile cache memory, and identifying a size of the management units in the non-volatile cache memory. The method further includes identifying write requests to write data to the non-volatile cache memory, sequentially writing to the non-volatile cache memory the write data for the identified write requests, to sequentially arranged locations in an address space of the non-volatile cache memory, and storing in memory metadata that maps the addresses or storage offsets of the write data to respective locations in the address space of the non-volatile cache memory.

Abstract: A determining unit selects one storage device each from storage devices of an external storage apparatus and storage devices of a storage apparatus to which the determining unit belongs. At this point, based on a copy request, the determining unit preferentially selects, within each of the external storage apparatus and the storage apparatus, a storage device including a larger number of logical volumes (LVs) which belong to copy unexecuted LV pairs compared to other storage devices therein. Further, the determining unit determines, as a copy execution target, a copy unexecuted LV pair in which a LV provided in one of the selected two storage devices is a copy source and a LV provided in the other storage device is a copy destination. A copy unit copies data stored in the copy source LV, which belongs to the determined LV pair, to the copy destination LV of the LV pair.

Abstract: Techniques for implementing a data queuing and/or caching scheme for optimizing data storage are described herein. Data write requests are received and processed by at least queuing the requests and/or associated data for recording upon one or more data storage devices. The order within the queue, as well as the order in which the queued requests are serviced, may, in some embodiments, be optimized. The stored data are verified by determining the position of a write pointer implemented by the one or more data storage devices relative to the contents and/or position of the queued data requests.

Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.

Abstract: The present invention discloses a data caching method and apparatus, and relates to the field of network applications. The method includes: receiving a first data request; writing target data in the first data request into an on-chip Cache, and counting a storage time of the target data in the on-chip cache; enabling a delay expiry identifier of the target data when the storage time of the target data in the Cache reaches a preset delay time; and releasing the target data when the delay expiry identifier of the target data is in an enabled state and processing of the target data is complete.

Abstract: Aspects of the subject technology relate to a computer-implemented process, including steps for compiling a first method call at a first call site in code of an object-oriented language, wherein the first call site is associated with a first selector, referencing a global cache comprising a plurality of per-selector caches, wherein each of the per-selector caches is indexed based on a corresponding selector identification and identifying a first per-selector cache, from among the plurality of per-selector caches, using the first selector. In certain aspects, the process can further include steps for invoking a method on a first object by performing a lookup in the first per-selector cache using a class associated with the first object to determine if a first target function exists in the first per-selector cache. Systems and computer readable media are also provided.