Abstract: The invention relates to the modeling of a complex system wherein units such as data and/or products are received, processed and forwarded in event chains of the system. Said modeling uses a defined set of basic types at the lowest description level for representation of the units and in order to describe the interaction therebetween. Each basic type processes data representing values of characteristics of the above-mentioned units.

Abstract: The present invention provides methods and systems for using a design element in a graphical model to represent and identify a precondition for use by a verification tool in verifying an executable form of the design represented by the graphical model. The precondition design element provides a specification of a verification constraint without affecting the behavior of the design. The constraint is to be applied by the verification tool in verifying the design. As such, the precondition design element of the present invention provides a mechanism and formalism in a model-based design approach that is used to constrain automatically generated tests or verification of the design represented by the graphical model.

Abstract: Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.

Abstract: A method provides early estimation of product life using accelerated stress testing data. In an embodiment, data measured from a product operating in a first, high-stress environment is used to predict how long the product will operate in a second, normal operating environment before failure, using an exponential acceleration model. An additional feature of the present invention provides a quantified indication of how much the product has improved from a redesign.

Abstract: Determining a geometric error of a polygon in a subdivision surface includes obtaining a value that corresponds to an angular difference between a face vector normal to a face of the polygon and a vertex vector normal to a vertex of the polygon, determining a geometric error associated with the vertex based on the value and the face vector, and calculating the geometric error of the polygon using the geometric error associated with the vertex.

Abstract: A method for accelerating hardware simulation is presented wherein cycle based simulations of digital system designs are generated by raising the level of abstraction in a hardware simulation environment. Behavioral models of the digital system components are created in a high level general purpose programming language. Function calls created in a high level general purpose programming language provide a transaction based communication interface. During a simulation of the system design, the behavioral models communicate with each other through the transaction based communication interface. Additionally, the behavioral models employ an execute and update method of instruction processing that generates cycle accurate information for the simulation.

Abstract: A method is provided for exploring alternative architectures for partitioning computer system resources to execute multiple task specifications. An initial master task graph is formed from the multiple task specifications, the initial master task graph including at least one hierarchical task with pointers to either AND sub-task graphs or XOR sub-task graphs. The initial master task graph is processed to provide a selected number of final master task graphs, each of the final master task graphs comprising a list of AND task graphs. A family of architectures is generated for each of the final master task graphs, each of the architectures generated for a given master task graph being capable of executing every AND task graph included therein.

Abstract: This invention presents a method and system for industrializing a designed part. This invention includes selecting a parting surface to divide the designed part, which includes a functional specification, into a first side and a second side, and selecting a draft angle. A change is computed in the first side and the second side using the selected draft angle. During the computation, the functional specification is maintained and the first side and second side meet on the parting surface. A face and a pulling direction can also be selected on the designed part. The selected face can be parallel to the pulling direction for the first side. Faces adjacent to the selected face can also be used in the computation. Once computed, the industrialized designed part can be displayed. An optimal blend draft method or a driving/driven blend draft method can be selected to compute the designed part.

Abstract: An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.

Abstract: The basic available command library of the run-time system (RTS1-RTS4) of a universal motion control (combined SPS/NC control) can be expanded dynamically and according to the user's specific requirements by loading technology packets TP (with corresponding technology object types TO). Thus, a dynamic scaling of a universal motion control UMC is possible. Due to a consistent integration and communication platform API, the functionality of extremely prepared technology packets TP can also be integrated into the control.