Patents Examined by Paul Patton
  • Patent number: 10367042
    Abstract: A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed outside the display area in the element substrate. A first metal layer is disposed on the reverse side of the element substrate at a position opposite to the display area. A second metal layer is disposed with a space between the first metal layer and the second metal layer on the reverse side of the element substrate at a position opposite to the driver IC.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: July 30, 2019
    Assignee: Japan Display Inc.
    Inventors: Ryoichi Ito, Toshihiro Sato
  • Patent number: 10084043
    Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy, Chandra S. Mohapatra, Sanaz K. Gardner, Marko Radosavljevic, Glenn A. Glass
  • Patent number: 10079359
    Abstract: An organic light emitting diode according to the present disclosure includes a first electrode, a second electrode overlapping the first electrode, and an emission layer disposed between the first electrode and the second electrode. The second electrode includes a bottom region and a top region. The bottom region includes a MgAg alloy including more Mg than Ag. The top region includes a AgMg alloy including more Ag than Mg.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eun Ho Kim, Da Hye Kim, Su Hwan Lee, Sang Yeol Kim
  • Patent number: 10068926
    Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10062815
    Abstract: A light emitting device includes a carrier, a light emitting chip, and a covering part disposed on the carrier. The carrier includes a board, a guiding metal layer, and a sealing material. The board has a first surface, a second surface, and a through vent that is divided into a first partial hole and a second partial hole. The first partial hole extends from the first surface to the second partial hole, and the second partial hole extends from the second surface to the first partial hole. The guiding metal layer is formed on the second surface and in the second partial hole, and covers the sidewall of the second partial hole. The guiding metal layer extends from the second partial hole to the second surface, and does not cover the sidewall of the first partial hole and the first surface. The sealing material seals the second partial hole.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 28, 2018
    Assignee: UNISTARS CORPORATION
    Inventors: Hsin-Hsien Hsieh, Shang-Yi Wu
  • Patent number: 10056478
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Wei Tsai, King-Yuen Wong, Chih-Wen Hsiung, Ming-Cheng Lin
  • Patent number: 10032831
    Abstract: A display device preventing light leak to an adjacent pixel and thus to prevent color mixing to improve image quality is provided. An organic EL display device includes a plurality of pixels. The plurality of pixels each include a light emitting element; the light emitting element includes a pixel electrode, a common electrode, an EL common layer, and a light emitting layer; the EL common layer and the light emitting layer are provided between the pixel electrode and the common electrode; the EL common layer covers a main surface and an end of the pixel electrode; the pixel electrode is provided on an insulating layer; and the common electrode is in contact with the insulating layer between the plurality of pixels.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 24, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10032918
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Ryo Tokumaru, Yasumasa Yamane, Kiyofumi Ogino, Taichi Endo, Hajime Kimura
  • Patent number: 10011476
    Abstract: A MEMS apparatus includes a substrate, a cover disposed on the substrate, a movable mass disposed on the substrate, and an impact absorber disposed on the cover. The impact absorber includes a restraint, a stationary stopper disposed on a lower surface of the cover, a movable stopper, elastic elements connecting the restraint and the movable stopper, a supporting element connecting the restraint and the stationary stopper, and a space disposed between the stationary stopper and the movable stopper. The impact absorber is adapted to prevent the movable mass from impacting the cover. In addition, the supporting element may be made of an electrical insulation material to reduce electrostatic interaction between the movable mass and the movable stopper.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 3, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Wen Hsu, Chin-Fu Kuo, Chao-Ta Huang
  • Patent number: 10014411
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 10002955
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: June 19, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Wei Tsai, King-Yuen Wong, Chih-Wen Hsiung, Ming-Cheng Lin
  • Patent number: 10002872
    Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The horizontal address lines and the vertical address lines comprise oppositely-doped semiconductor materials.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: June 19, 2018
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 10001678
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9991248
    Abstract: A first semiconductor package of a POP structure has a first body and a plurality of first solder balls. A second semiconductor package of the POP structure has a second body and a plurality of second solder balls. A stand-off mechanism is utilized to maintain a minimum gap between the first body and the second body while a reflow soldering process is performed. By performing the reflow soldering process, the first solder balls and the second solder balls are heated and engaging with one another so as to solder the first solder balls and the second solder balls to form a plurality of interposer solder balls. Each interposer solder ball has a height substantially equal to the minimum gap and a cross sectional width less than a pitch between two adjacent interposer solder balls. Thereby, the POP structure would be a fine pitch package.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 5, 2018
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventor: Wen-Jeng Fan
  • Patent number: 9985212
    Abstract: A method for making semiconducting layer includes: providing a carbon nanotube film; providing a conductive substrate and applying an insulating layer on the conductive substrate; laying the carbon nanotube film on a surface of the insulating layer, and placing the carbon nanotube film under a scanning electron microscope; adjusting the scanning electron microscope with an accelerating voltage ranging 5˜20 KV, and taking photos of the carbon nanotube film with the scanning electron microscope; obtaining a photo of the carbon nanotube film, wherein the photo shows the plurality of carbon nanotubes and a background, a plurality of first carbon nanotubes have lighter color than a color of the background, a plurality of second carbon nanotubes have deeper color than the color of the background; and removing the plurality of first carbon nanotubes.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 29, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Dong-Qi Li, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 9978840
    Abstract: In a first main surface of a silicon carbide substrate, a second trench having a second side surface which connects to the first main surface and is in contact with a third impurity region and a second impurity region and a second bottom portion continuous to the second side surface is formed. A fourth impurity region has a first region arranged between a second main surface and the second impurity region and a second region connecting the second bottom portion of the second trench and the first region to each other. A first electrode is electrically connected to the third impurity region on a side of the first main surface and is in contact with the second region at the second bottom portion of the second trench.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 22, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromu Shiomi
  • Patent number: 9978881
    Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
  • Patent number: 9978783
    Abstract: A semiconductor device includes first and second photo-electric conversion elements, each having a light-receiving surface, disposed adjacent to each other, each outputting a light current that is a current corresponding to an intensity of received light, a first filter disposed on the light-receiving surface of the first photo-electric conversion element, a second filter disposed on the light-receiving surface of the second photo-electric conversion element, and a third filter disposed on the light-receiving surface of the second photo-electric conversion element and being in contact with the second filter, one end of the second filter and one end of the third filter overlapping one end of the first filter at a vicinity of a boundary between the first photo-electric conversion element and the second photo-electric conversion element.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 22, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masao Okihara
  • Patent number: 9978777
    Abstract: A TFT array panel of a display device includes a first substrate, a first electrode disposed on the first substrate, a first insulating layer including a first hole, the first insulating layer disposed on the first electrode, a second insulating layer disposed on the first insulating layer and including a second hole corresponding to the first hole, and a capping layer including a first inner portion, the capping layer disposed on an inner lateral surface forming the second hole, where an end portion of the first inner portion disposed in the second hole is separated from the first electrode.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae An Seo, Su Bin Bae, Yu-Gwang Jeong, Hyun Min Cho, Shin Il Choi, Jin Hwan Choi
  • Patent number: 9972573
    Abstract: Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 15, 2018
    Assignee: Invensas Corporation
    Inventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba